#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
#ifdef CONFIG_36BIT
#define CONFIG_PHYS_64BIT
#endif
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
#define CONFIG_SYS_CPLD_BASE 0xffa00000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
-#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
+#if defined(CONFIG_P2020RDB)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
+#else
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
+#endif
#elif defined(CONFIG_NAND)
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
#ifdef CONFIG_QE
/* QE microcode/firmware address */
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000
+#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#endif /* CONFIG_QE */
#endif
#endif
+#if defined(CONFIG_P1020RDB_PD)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
+
#define CONFIG_MMC
#ifdef CONFIG_MMC