]> git.sur5r.net Git - u-boot/blobdiff - include/configs/pcs440ep.h
Merge branch '080202_at91rm9200dk' of git://linux-arm.org/u-boot-armdev
[u-boot] / include / configs / pcs440ep.h
index 7653ba1d2457c64ee4ab7b6c494b924db39e17cc..07fc23e5e73724780c21bbe9c6e580287e145704 100644 (file)
@@ -66,7 +66,7 @@
  *----------------------------------------------------------------------*/
 #define CFG_INIT_RAM_DCACHE    1               /* d-cache as init ram  */
 #define CFG_INIT_RAM_ADDR      0x70000000              /* DCache       */
-#define CFG_INIT_RAM_END       (8 << 10)
+#define CFG_INIT_RAM_END       (4 << 10)
 #define CFG_GBL_DATA_SIZE      256                     /* num bytes initial data*/
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
 /*-----------------------------------------------------------------------
  * PPC440 GPIO Configuration
  */
-#define CFG_440_GPIO_TABLE { /*          Out                  GPIO     Alternate1      Alternate2   Alternate3 */ \
+#define CFG_4xx_GPIO_TABLE { /*          Out                  GPIO     Alternate1      Alternate2   Alternate3 */ \
 {                                                                                      \
 /* GPIO Core 0 */                                                                      \
 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO0   EBC_ADDR(7)     DMA_REQ(2)      */ \
 }                                                                                      \
 }
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE                (32<<10) /* For AMCC 440 CPUs                   */
-#define CFG_CACHELINE_SIZE     32      /* ...                  */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
-#endif
-
 /*
  * Internal Definitions
  *