DaVinci DM6467: Enhance board Support

[u-boot] / include / configs / r2dplus.h

diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index 6fa1eafde7ddd054a5d562857196c6b906eeb01b..8689513fb784b5127d1573c31b84bd5bf18d01ad 100644 (file)
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h
@@ -24,6 +24,7 @@
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_EXT2
 #define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_SH_ZIMAGEBOOT
 
 /* SCIF */
 #define CONFIG_SCIF_CONSOLE    1
@@ -49,7 +50,7 @@
 #define CONFIG_SYS_BAUDRATE_TABLE      { 115200, 57600, 38400, 19200, 9600 }
 
 #define CONFIG_SYS_MEMTEST_START       (CONFIG_SYS_SDRAM_BASE)
-#define CONFIG_SYS_MEMTEST_END         (TEXT_BASE - 0x100000)
+#define CONFIG_SYS_MEMTEST_END         (CONFIG_SYS_TEXT_BASE - 0x100000)
 
 #define CONFIG_SYS_LOAD_ADDR           (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
 /* Address of u-boot image in Flash */
@@ -58,7 +59,6 @@
 /* Size of DRAM reserved for malloc() use */
 #define CONFIG_SYS_MALLOC_LEN          (1024 * 1024)
 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE       (256)
 #define CONFIG_SYS_BOOTMAPSZ           (8 * 1024 * 1024)
 
 /*
@@ -80,8 +80,8 @@
  * SuperH Clock setting
  */
 #define CONFIG_SYS_CLK_FREQ    60000000
-#define TMU_CLK_DIVIDER                4
-#define CONFIG_SYS_HZ                  (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CONFIG_SYS_TMU_CLK_DIV         4
+#define CONFIG_SYS_HZ          1000
 #define        CONFIG_SYS_PLL_SETTLING_TIME    100/* in us */
 
 /*
@@ -96,6 +96,7 @@
 #define CONFIG_SYS_ATA_DATA_OFFSET     0x1000  /* data reg offset */
 #define CONFIG_SYS_ATA_REG_OFFSET      0x1000  /* reg offset */
 #define CONFIG_SYS_ATA_ALT_OFFSET      0x800   /* alternate register offset */
+#define CONFIG_IDE_SWAP_IO
 
 /*
  * SuperH PCI Bridge Configration
@@ -123,7 +124,5 @@
  */
 #define CONFIG_NET_MULTI
 #define CONFIG_RTL8139
-#define _IO_BASE               0x00000000
-#define KSEG1ADDR(x)           (x)
 
 #endif /* __CONFIG_H */