* SuperH Clock setting
*/
#define CONFIG_SYS_CLK_FREQ 60000000
-#define TMU_CLK_DIVIDER 4
+#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
+#define CONFIG_IDE_SWAP_IO
/*
* SuperH PCI Bridge Configration
*/
#define CONFIG_NET_MULTI
#define CONFIG_RTL8139
-#define _IO_BASE 0x00000000
-#define KSEG1ADDR(x) (x)
#endif /* __CONFIG_H */