Merge branch 'master' into next

[u-boot] / include / configs / sbc2410x.h

diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h
index af0018772ce65a9bc5635c5cb0a2ae7416714904..025ad0953c2807115f86aa80897fedb888326e68 100644 (file)
--- a/include/configs/sbc2410x.h
+++ b/include/configs/sbc2410x.h
@@ -2,7 +2,7 @@
  * (C) Copyright 2002
  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  * Marius Groeger <mgroeger@sysgo.de>
- * Gary Jennejohn <gj@denx.de>
+ * Gary Jennejohn <garyj@denx.de>
  * David Mueller <d.mueller@elsoft.ch>
  *
  * Modified for the friendly-arm SBC-2410X by
@@ -43,9 +43,10 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_ARM920T         1       /* This is an ARM920T Core      */
-#define        CONFIG_S3C2410          1       /* in a SAMSUNG S3C2410 SoC     */
-#define CONFIG_SBC2410X                1       /* on a friendly-arm SBC-2410X Board  */
+#define CONFIG_ARM920T 1       /* This is an ARM920T Core      */
+#define CONFIG_S3C24X0 1       /* in a SAMSUNG S3C24x0-type SoC        */
+#define CONFIG_S3C2410 1       /* specifically a SAMSUNG S3C2410 SoC   */
+#define CONFIG_SBC2410X        1       /* on a friendly-arm SBC-2410X Board  */
 
 /* input clock of PLL */
 #define CONFIG_SYS_CLK_FREQ    12000000/* the SBC2410X has 12MHz input clock */
@@ -63,9 +64,10 @@
 /*
  * Hardware drivers
  */
-#define CONFIG_DRIVER_CS8900   1       /* we have a CS8900 on-board */
-#define CS8900_BASE            0x19000300
-#define CS8900_BUS16           1 /* the Linux driver does accesses as shorts */
+#define CONFIG_NET_MULTI
+#define CONFIG_CS8900          /* we have a CS8900 on-board */
+#define CONFIG_CS8900_BASE     0x19000300
+#define CONFIG_CS8900_BUS16    /* the Linux driver does accesses as shorts */
 
 /*
  * select serial console configuration
@@ -138,9 +140,7 @@
 
 #define        CONFIG_SYS_LOAD_ADDR            0x33000000      /* default load address */
 
-/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
-/* it to wrap 100 times (total 1562500) to get 1 sec. */
-#define        CONFIG_SYS_HZ                   1562500
+#define        CONFIG_SYS_HZ                   1000
 
 /* valid baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
@@ -201,29 +201,6 @@
 #if defined(CONFIG_CMD_NAND)
 #define CONFIG_NAND_S3C2410
 #define CONFIG_SYS_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN    0x00
-#define NAND_MAX_FLOORS 1
-
-#define NAND_WAIT_READY(nand)  NF_WaitRB()
-#define NAND_DISABLE_CE(nand)  NF_SetCE(NFCE_HIGH)
-#define NAND_ENABLE_CE(nand)   NF_SetCE(NFCE_LOW)
-#define WRITE_NAND_COMMAND(d, adr)     NF_Cmd(d)
-#define WRITE_NAND_COMMANDW(d, adr)    NF_CmdW(d)
-#define WRITE_NAND_ADDRESS(d, adr)     NF_Addr(d)
-#define WRITE_NAND(d, adr)             NF_Write(d)
-#define READ_NAND(adr)                 NF_Read()
-/* the following functions are NOP's because S3C24X0 handles this in hardware */
-#define NAND_CTL_CLRALE(nandptr)
-#define NAND_CTL_SETALE(nandptr)
-#define NAND_CTL_CLRCLE(nandptr)
-#define NAND_CTL_SETCLE(nandptr)
-/* #undef CONFIG_MTD_NAND_VERIFY_WRITE */
 #endif /* CONFIG_CMD_NAND */
 
 #define CONFIG_SETUP_MEMORY_TAGS