85xx: Convert MPC8544 DS to new TLB setup

[u-boot] / include / configs / sc520_cdp.h

diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h
index 292b4bf3f12ae1c9864413e4e76dd979ce2e03f9..8491d97ae421607a70736e694d5f7ff876be6f44 100644 (file)
--- a/include/configs/sc520_cdp.h
+++ b/include/configs/sc520_cdp.h
@@ -37,7 +37,7 @@
 #define CONFIG_SC520           1       /* Include support for AMD SC520 */
 #define CONFIG_ALI152X         1       /* Include support for Ali 152x SIO */
 
-#define CFG_SDRAM_PRECHARGE_DELAY 6     /* 6T */       
+#define CFG_SDRAM_PRECHARGE_DELAY 6     /* 6T */
 #define CFG_SDRAM_REFRESH_RATE    78    /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
 #define CFG_SDRAM_RAS_CAS_DELAY   3     /* 3T */
 
@@ -64,24 +64,37 @@
  */
 #define CONFIG_MALLOC_SIZE     (CFG_ENV_SIZE + 128*1024)
 
-
 #define CONFIG_BAUDRATE                9600
 
-#define CONFIG_COMMANDS         (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET | CFG_CMD_EEPROM)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
 
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_EEPROM
 
 #define CONFIG_BOOTDELAY       15
 #define CONFIG_BOOTARGS        "root=/dev/mtdblock0 console=ttyS0,9600"
 /* #define CONFIG_BOOTCOMMAND  "bootm 38000000" */
 
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE   115200          /* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX  2               /* which serial port to use */
 #endif
 
-
 /*
  * Miscellaneous configurable options
  */
@@ -104,7 +117,6 @@
                                                /* valid baudrates */
 #define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200 }
 
-
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
@@ -113,8 +125,6 @@
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-
-
 #define CFG_MAX_FLASH_BANKS    3       /* max number of memory banks           */
 #define CFG_MAX_FLASH_SECT     64      /* max number of sectors on one chip    */
 
@@ -123,23 +133,35 @@
 #define CFG_FLASH_WRITE_TOUT   (2*CFG_HZ) /* Timeout for Flash Write */
 
 #define CONFIG_SPI_EEPROM      /* Support for SPI EEPROMs (AT25128) */
-#define CONFIG_MW_EEPROM       /* Support for MicroWire EEPROMs (AT93LC46) */ 
-
+#define CONFIG_MW_EEPROM       /* Support for MicroWire EEPROMs (AT93LC46) */
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
-
 /* Environment in EEPROM */
 #define CFG_ENV_IS_IN_EEPROM   1
 #define CONFIG_SPI
 #define CFG_ENV_SIZE          0x4000   /* Total Size of Environment EEPROM 16k is SPI is used or 128 bytes if MW is used*/
-#define CFG_ENV_OFFSET         0      
+#define CFG_ENV_OFFSET         0
 #define CONFIG_SC520_CDP_USE_SPI  /* Store configuration in the SPI part */
 #undef CONFIG_SC520_CDP_USE_MW    /* Store configuration in the MicroWire part */
 #define CONFIG_SPI_X 1
-#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS     1           /*  */
+
+/*
+ * JFFS2 partitions
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV               "nor0"
+#define CONFIG_JFFS2_PART_SIZE         0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET       0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT         "nor0=SC520CDP Flash Bank #0"
+#define MTDPARTS_DEFAULT       "mtdparts=SC520CDP Flash Bank #0:-(jffs2)"
+*/
 
 /*-----------------------------------------------------------------------
  * Device drivers
@@ -157,7 +179,7 @@
 #define CFG_IDE_MAXDEVICE      (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 
 #define CFG_ATA_IDE0_OFFSET    0x01F0  /* ide0 offste */
-//#define CFG_ATA_IDE1_OFFSET  0x0170  /* ide1 offset */
+/*#define CFG_ATA_IDE1_OFFSET  0x0170  /###* ide1 offset */
 #define CFG_ATA_DATA_OFFSET    0       /* data reg offset      */
 #define CFG_ATA_REG_OFFSET     0       /* reg offset */
 #define CFG_ATA_ALT_OFFSET     0x200   /* alternate register offset */
@@ -167,6 +189,15 @@
 #undef  CONFIG_IDE_RESET               /* reset for ide unsupported... */
 #undef  CONFIG_IDE_RESET_ROUTINE       /* no special reset function */
 
+/************************************************************
+*SATA/Native Stuff
+************************************************************/
+#define CFG_SATA_SUPPORTED      1
+#define CFG_SATA_MAXBUS         2       /*Max Sata buses supported */
+#define CFG_SATA_DEVS_PER_BUS   2      /*Max no. of devices per bus/port */
+#define CFG_SATA_MAXDEVICES     (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS)
+#define CFG_ATA_PIIX            1       /*Supports ata_piix driver */
+
 /************************************************************
  * ATAPI support (experimental)
  ************************************************************/
@@ -186,8 +217,6 @@
 #define CONFIG_I8042_KBD
 #define CFG_ISA_IO 0
 
-
-
 /************************************************************
  * RTC
  ***********************************************************/
@@ -202,9 +231,8 @@
 #define CONFIG_PCI_SCAN_SHOW
 
 #define        CFG_FIRST_PCI_IRQ   10
-#define        CFG_SECOND_PCI_IRQ  9 
-#define CFG_THIRD_PCI_IRQ   11 
+#define        CFG_SECOND_PCI_IRQ  9
+#define CFG_THIRD_PCI_IRQ   11
 #define        CFG_FORTH_PCI_IRQ   15
 
-
 #endif /* __CONFIG_H */