#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
-#define CONFIG_SYS_GENERIC_BOARD
/* Virtual target or real hardware */
#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
/*
* Cache
*/
-#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
/*
* QSPI support
*/
-#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
#define CONFIG_CADENCE_QSPI
/* Enable multiple SPI NOR flash manufacturers */
#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */
#define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_SPI_FLASH_MTD
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nor0=ff705000.spi"
+#endif
/* QSPI reference clock */
#ifndef __ASSEMBLY__
unsigned int cm_get_qspi_controller_clk_hz(void);
#endif
#define CONFIG_CQSPI_DECODER 0
#define CONFIG_CMD_SF
-#endif
+#define CONFIG_SPI_FLASH_BAR
-#ifdef CONFIG_OF_CONTROL /* DW SPI is controlled via DT */
+/*
+ * Designware SPI support
+ */
#define CONFIG_DESIGNWARE_SPI
#define CONFIG_CMD_SPI
-#endif
/*
* Serial Driver
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 4096
/*