armv8/ls1043a: Enable secondary cores

[u-boot] / include / configs / socfpga_common.h

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index c64c7ed42075a20179c43c2648d652968ad93548..3374683911570890e8e35c854d92732543ae0b88 100644 (file)
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -6,7 +6,6 @@
 #ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
 #define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
 
-#define CONFIG_SYS_GENERIC_BOARD
 
 /* Virtual target or real hardware */
 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
@@ -73,7 +72,6 @@
 /*
  * Cache
  */
-#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
 #define CONFIG_SYS_CACHELINE_SIZE 32
 #define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE          SOCFPGA_MPUL2_ADDRESS
@@ -192,7 +190,6 @@ unsigned int cm_get_l4_sp_clk_hz(void);
 /*
  * QSPI support
  */
-#ifdef CONFIG_OF_CONTROL       /* QSPI is controlled via DT */
 #define CONFIG_CADENCE_QSPI
 /* Enable multiple SPI NOR flash manufacturers */
 #define CONFIG_SPI_FLASH_STMICRO       /* Micron/Numonyx flash */
@@ -212,12 +209,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_CQSPI_DECODER           0
 #define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH_BAR
-#endif
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)      /* DW SPI is controlled via DT */
+/*
+ * Designware SPI support
+ */
 #define CONFIG_DESIGNWARE_SPI
 #define CONFIG_CMD_SPI
-#endif
 
 /*
  * Serial Driver
@@ -283,7 +280,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
-#define CONFIG_ENV_IS_NOWHERE
 #define CONFIG_ENV_SIZE                        4096
 
 /*