Prepare v2018.07-rc1

[u-boot] / include / configs / socfpga_common.h

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index d343a6ec0a32907ac85c608a1515c2c44f7a9635..acac4a7108335bf768372949873515d1abb04016 100644 (file)
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -1,18 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 #ifndef __CONFIG_SOCFPGA_COMMON_H__
 #define __CONFIG_SOCFPGA_COMMON_H__
 
-/* Virtual target or real hardware */
-#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
-
 /*
  * High level configuration
  */
-#define CONFIG_DISPLAY_BOARDINFO_LATE
 #define CONFIG_CLOCKS
 
 #define CONFIG_SYS_BOOTMAPSZ           (64 * 1024 * 1024)
@@ -37,29 +32,19 @@
 #define CONFIG_SYS_INIT_RAM_ADDR       0xFFE00000
 #define CONFIG_SYS_INIT_RAM_SIZE       0x40000 /* 256KB */
 #endif
-#define CONFIG_SYS_INIT_SP_OFFSET              \
-       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR                        \
-       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_SYS_TEXT_BASE           0x08000040
-#else
-#define CONFIG_SYS_TEXT_BASE           0x01000040
-#endif
 
 /*
  * U-Boot general configurations
  */
-#define CONFIG_SYS_LONGHELP
 #define CONFIG_SYS_CBSIZE      1024            /* Console I/O buffer size */
                                                /* Print buffer size */
 #define CONFIG_SYS_MAXARGS     32              /* Max number of command args */
 #define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE
                                                /* Boot argument buffer size */
-#define CONFIG_AUTO_COMPLETE                   /* Command auto complete */
-#define CONFIG_CMDLINE_EDITING                 /* Command history etc */
 
 #ifndef CONFIG_SYS_HOSTNAME
 #define CONFIG_SYS_HOSTNAME    CONFIG_SYS_BOARD
@@ -88,7 +73,7 @@
 /*
  * Ethernet on SoC (EMAC)
  */
-#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+#ifdef CONFIG_CMD_NET
 #define CONFIG_DW_ALTDESCRIPTOR
 #define CONFIG_MII
 #endif
@@ -107,11 +92,7 @@
 #define CONFIG_SYS_TIMERBASE           SOCFPGA_OSC1TIMER0_ADDRESS
 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 #define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMERBASE + 0x4)
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_SYS_TIMER_RATE          2400000
-#else
 #define CONFIG_SYS_TIMER_RATE          25000000
-#endif
 
 /*
  * L4 Watchdog
@@ -146,6 +127,7 @@
 /*
  * I2C support
  */
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_BASE            SOCFPGA_I2C0_ADDRESS
 #define CONFIG_SYS_I2C_BASE1           SOCFPGA_I2C1_ADDRESS
@@ -166,6 +148,7 @@
 unsigned int cm_get_l4_sp_clk_hz(void);
 #define IC_CLK                         (cm_get_l4_sp_clk_hz() / 1000000)
 #endif
+#endif /* CONFIG_DM_I2C */
 
 /*
  * QSPI support
@@ -190,17 +173,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  * Serial Driver
  */
 #define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE    -4
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_SYS_NS16550_CLK         1000000
-#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#define CONFIG_SYS_NS16550_COM1                SOCFPGA_UART0_ADDRESS
-#define CONFIG_SYS_NS16550_CLK         100000000
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-#define CONFIG_SYS_NS16550_COM1        SOCFPGA_UART1_ADDRESS
-#define CONFIG_SYS_NS16550_CLK         50000000
-#endif
-#define CONFIG_CONS_INDEX              1
 
 /*
  * USB
@@ -210,8 +182,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  * USB Gadget (DFU, UMS)
  */
 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
-#define CONFIG_USB_FUNCTION_MASS_STORAGE
-
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE   (16 * 1024 * 1024)
 #define DFU_DEFAULT_POLL_TIMEOUT       300
 
@@ -256,18 +226,34 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 /*
  * SPL
  *
- * SRAM Memory layout:
+ * SRAM Memory layout for gen 5:
  *
  * 0xFFFF_0000 ...... Start of SRAM
  * 0xFFFF_xxxx ...... Top of stack (grows down)
  * 0xFFFF_yyyy ...... Malloc area
  * 0xFFFF_zzzz ...... Global Data
  * 0xFFFF_FF00 ...... End of SRAM
+ *
+ * SRAM Memory layout for Arria 10:
+ * 0xFFE0_0000 ...... Start of SRAM (bottom)
+ * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
+ * 0xFFEy_yyyy ...... Global Data
+ * 0xFFEz_zzzz ...... Malloc area (grows up to top)
+ * 0xFFE3_FFFF ...... End of SRAM (top)
  */
-#define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TEXT_BASE           CONFIG_SYS_INIT_RAM_ADDR
 #define CONFIG_SPL_MAX_SIZE            CONFIG_SYS_INIT_RAM_SIZE
 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+/* SPL memory allocation configuration, this is for FAT implementation */
+#ifndef CONFIG_SYS_SPL_MALLOC_START
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x00010000
+#define CONFIG_SYS_SPL_MALLOC_START    (CONFIG_SYS_INIT_RAM_SIZE - \
+                                        CONFIG_SYS_SPL_MALLOC_SIZE + \
+                                        CONFIG_SYS_INIT_RAM_ADDR)
+#endif
+#endif
+
 /* SPL SDMMC boot support */
 #ifdef CONFIG_SPL_MMC_SUPPORT
 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
@@ -282,7 +268,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 
 /* SPL QSPI boot support */
 #ifdef CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_LOAD
 #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x40000
 #endif
 
@@ -295,11 +280,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 /*
  * Stack setup
  */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SPL_STACK               CONFIG_SYS_INIT_SP_ADDR
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SPL_STACK               CONFIG_SYS_SPL_MALLOC_START
+#endif
 
 /* Extra Environment */
 #ifndef CONFIG_SPL_BUILD
-#include <config_distro_defaults.h>
 
 #ifdef CONFIG_CMD_DHCP
 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
@@ -307,7 +295,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define BOOT_TARGET_DEVICES_DHCP(func)
 #endif
 
-#ifdef CONFIG_CMD_PXE
+#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
 #else
 #define BOOT_TARGET_DEVICES_PXE(func)