nios2: Split timer code into timer.c

[u-boot] / include / configs / socfpga_common.h

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 60a602517f97e4793fe7796e1d606ad862d5396a..cece0950e29769608f95730eed34f64657deb883 100644 (file)
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -23,6 +23,8 @@
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_CLOCKS
 
+#define CONFIG_CRC32_VERIFY
+
 #define CONFIG_FIT
 #define CONFIG_OF_LIBFDT
 #define CONFIG_SYS_BOOTMAPSZ           (64 * 1024 * 1024)
@@ -71,7 +73,6 @@
 /*
  * Cache
  */
-#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
 #define CONFIG_SYS_CACHELINE_SIZE 32
 #define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE          SOCFPGA_MPUL2_ADDRESS
@@ -190,12 +191,17 @@ unsigned int cm_get_l4_sp_clk_hz(void);
 /*
  * QSPI support
  */
-#ifdef CONFIG_OF_CONTROL       /* QSPI is controlled via DT */
 #define CONFIG_CADENCE_QSPI
 /* Enable multiple SPI NOR flash manufacturers */
 #define CONFIG_SPI_FLASH_STMICRO       /* Micron/Numonyx flash */
 #define CONFIG_SPI_FLASH_SPANSION      /* Spansion flash */
+#ifndef CONFIG_SPL_BUILD
 #define CONFIG_SPI_FLASH_MTD
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT                 "nor0=ff705000.spi"
+#endif
 /* QSPI reference clock */
 #ifndef __ASSEMBLY__
 unsigned int cm_get_qspi_controller_clk_hz(void);
@@ -203,12 +209,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #endif
 #define CONFIG_CQSPI_DECODER           0
 #define CONFIG_CMD_SF
-#endif
+#define CONFIG_SPI_FLASH_BAR
 
-#ifdef CONFIG_OF_CONTROL       /* DW SPI is controlled via DT */
+/*
+ * Designware SPI support
+ */
 #define CONFIG_DESIGNWARE_SPI
 #define CONFIG_CMD_SPI
-#endif
 
 /*
  * Serial Driver
@@ -274,7 +281,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
-#define CONFIG_ENV_IS_NOWHERE
 #define CONFIG_ENV_SIZE                        4096
 
 /*
@@ -296,9 +302,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SYS_MALLOC_SIMPLE
 #endif
 
-#define CHUNKSZ_CRC32                  (1 * 1024)      /* FIXME: ewww */
-#define CONFIG_CRC32_VERIFY
-
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_WATCHDOG_SUPPORT
@@ -332,8 +335,4 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  */
 #define CONFIG_SPL_STACK               CONFIG_SYS_INIT_SP_ADDR
 
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_PARTITIONS
-#endif
-
 #endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */