Merge git://git.denx.de/u-boot-socfpga

[u-boot] / include / configs / socfpga_common.h

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 107c6d5b668403aa04976e41fcfa8a9130222e96..d343a6ec0a32907ac85c608a1515c2c44f7a9635 100644 (file)
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -15,8 +15,6 @@
 #define CONFIG_DISPLAY_BOARDINFO_LATE
 #define CONFIG_CLOCKS
 
-#define CONFIG_CRC32_VERIFY
-
 #define CONFIG_SYS_BOOTMAPSZ           (64 * 1024 * 1024)
 
 #define CONFIG_TIMESTAMP               /* Print image info with timestamp */
@@ -32,9 +30,13 @@
 #define CONFIG_SYS_MALLOC_LEN          (64 * 1024 * 1024)
 #define CONFIG_SYS_MEMTEST_START       PHYS_SDRAM_1
 #define CONFIG_SYS_MEMTEST_END         PHYS_SDRAM_1_SIZE
-
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SYS_INIT_RAM_ADDR       0xFFFF0000
 #define CONFIG_SYS_INIT_RAM_SIZE       0x10000
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_INIT_RAM_ADDR       0xFFE00000
+#define CONFIG_SYS_INIT_RAM_SIZE       0x40000 /* 256KB */
+#endif
 #define CONFIG_SYS_INIT_SP_OFFSET              \
        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR                        \
@@ -52,8 +54,6 @@
  */
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_SYS_CBSIZE      1024            /* Console I/O buffer size */
-#define CONFIG_SYS_PBSIZE      \
-       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
                                                /* Print buffer size */
 #define CONFIG_SYS_MAXARGS     32              /* Max number of command args */
 #define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE
@@ -65,9 +65,6 @@
 #define CONFIG_SYS_HOSTNAME    CONFIG_SYS_BOARD
 #endif
 
-#define CONFIG_CMD_PXE
-#define CONFIG_MENU
-
 /*
  * Cache
  */
@@ -94,17 +91,12 @@
 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 #define CONFIG_DW_ALTDESCRIPTOR
 #define CONFIG_MII
-#define CONFIG_AUTONEG_TIMEOUT         (15 * CONFIG_SYS_HZ)
-#define CONFIG_PHY_GIGE
 #endif
 
 /*
  * FPGA Driver
  */
 #ifdef CONFIG_CMD_FPGA
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_SOCFPGA
 #define CONFIG_FPGA_COUNT              1
 #endif
 
@@ -128,7 +120,7 @@
 #define CONFIG_DESIGNWARE_WATCHDOG
 #define CONFIG_DW_WDT_BASE             SOCFPGA_L4WD0_ADDRESS
 #define CONFIG_DW_WDT_CLOCK_KHZ                25000
-#define CONFIG_HW_WATCHDOG_TIMEOUT_MS  30000
+#define CONFIG_WATCHDOG_TIMEOUT_MSECS  30000
 #endif
 
 /*
@@ -146,19 +138,15 @@
  */
 #ifdef CONFIG_NAND_DENALI
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define CONFIG_SYS_NAND_MAX_CHIPS      1
 #define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_DENALI_ECC_SIZE    512
 #define CONFIG_SYS_NAND_REGS_BASE      SOCFPGA_NANDREGS_ADDRESS
 #define CONFIG_SYS_NAND_DATA_BASE      SOCFPGA_NANDDATA_ADDRESS
-#define CONFIG_SYS_NAND_BASE           (CONFIG_SYS_NAND_DATA_BASE + 0x10)
 #endif
 
 /*
  * I2C support
  */
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_BUS_MAX         4
 #define CONFIG_SYS_I2C_BASE            SOCFPGA_I2C0_ADDRESS
 #define CONFIG_SYS_I2C_BASE1           SOCFPGA_I2C1_ADDRESS
 #define CONFIG_SYS_I2C_BASE2           SOCFPGA_I2C2_ADDRESS
@@ -185,18 +173,14 @@ unsigned int cm_get_l4_sp_clk_hz(void);
 /* Enable multiple SPI NOR flash manufacturers */
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_SPI_FLASH_MTD
-#define CONFIG_CMD_MTDPARTS
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
-#define MTDIDS_DEFAULT                 "nor0=ff705000.spi.0"
 #endif
 /* QSPI reference clock */
 #ifndef __ASSEMBLY__
 unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_CQSPI_REF_CLK           cm_get_qspi_controller_clk_hz()
 #endif
-#define CONFIG_CQSPI_DECODER           0
-#define CONFIG_BOUNCE_BUFFER
 
 /*
  * Designware SPI support
@@ -207,20 +191,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  */
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    -4
-#define CONFIG_SYS_NS16550_COM1                SOCFPGA_UART0_ADDRESS
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_NS16550_CLK         1000000
-#else
+#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#define CONFIG_SYS_NS16550_COM1                SOCFPGA_UART0_ADDRESS
 #define CONFIG_SYS_NS16550_CLK         100000000
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_NS16550_COM1        SOCFPGA_UART1_ADDRESS
+#define CONFIG_SYS_NS16550_CLK         50000000
 #endif
 #define CONFIG_CONS_INDEX              1
 
 /*
  * USB
  */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2
-#endif
 
 /*
  * USB Gadget (DFU, UMS)
@@ -268,22 +252,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  * 5: rootfs              0x01000000      0x01000000      0
  *
  */
-#if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
-#define MTDPARTS_DEFAULT       "mtdparts=ff705000.spi.0:"\
-                               "1m(u-boot),"           \
-                               "256k(env1),"           \
-                               "256k(env2),"           \
-                               "14848k(boot),"         \
-                               "16m(rootfs),"          \
-                               "-@1536k(UBI)\0"
-#endif
-
-/* UBI and UBIFS support */
-#if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND)
-#define CONFIG_CMD_UBIFS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-#endif
 
 /*
  * SPL
@@ -298,7 +266,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  */
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TEXT_BASE           CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SPL_MAX_SIZE            (64 * 1024)
+#define CONFIG_SPL_MAX_SIZE            CONFIG_SYS_INIT_RAM_SIZE
 
 /* SPL SDMMC boot support */
 #ifdef CONFIG_SPL_MMC_SUPPORT
@@ -320,7 +288,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 
 /* SPL NAND boot support */
 #ifdef CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS  0
 #define CONFIG_SYS_NAND_U_BOOT_OFFS    0x40000
 #endif
@@ -334,6 +301,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #ifndef CONFIG_SPL_BUILD
 #include <config_distro_defaults.h>
 
+#ifdef CONFIG_CMD_DHCP
+#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
+#else
+#define BOOT_TARGET_DEVICES_DHCP(func)
+#endif
+
 #ifdef CONFIG_CMD_PXE
 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
 #else
@@ -349,7 +322,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define BOOT_TARGET_DEVICES(func) \
        BOOT_TARGET_DEVICES_MMC(func) \
        BOOT_TARGET_DEVICES_PXE(func) \
-       func(DHCP, dhcp, na)
+       BOOT_TARGET_DEVICES_DHCP(func)
 
 #include <config_distro_bootcmd.h>