85xx: Convert MPC8544 DS to new TLB setup

[u-boot] / include / configs / stxgp3.h

diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index 1f41cf7699e0ac4dac768d677790251c9a518754..047e1cf99a304e3465cae13e1d462dee6c0deb52 100644 (file)
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -51,6 +51,7 @@
 #define CONFIG_DDR_DLL                  /* possible DLL fix needed */
 #define CONFIG_DDR_2T_TIMING           /* Sets the 2T timing bit */
 
+#define CONFIG_FSL_LAW         1       /* Use common FSL init code */
 
 /* sysclk for MPC85xx
  */
@@ -234,12 +235,13 @@
 #define CONFIG_TSEC1_NAME      "TSEC0"
 #define CONFIG_TSEC2   1
 #define CONFIG_TSEC2_NAME      "TSEC1"
-#undef CONFIG_MPS85XX_FEC
 
 #define TSEC1_PHY_ADDR         2
 #define TSEC2_PHY_ADDR         4
 #define TSEC1_PHYIDX           0
 #define TSEC2_PHYIDX           0
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC2_FLAGS            TSEC_GIGABIT
 #define CONFIG_ETHPRIME                "TSEC0"
 
 #elif defined(CONFIG_ETHER_ON_FCC)     /* CPM FCC Ethernet */
@@ -356,13 +358,6 @@
  */
 #define CFG_BOOTMAPSZ          (8 << 20) /* Initial Memory map for Linux */
 
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE                32768
-#define CFG_CACHELINE_SIZE     32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value */
-#endif
-
 /*
  * Internal Definitions
  *
@@ -378,6 +373,7 @@
 
 /*Note: change below for your network setting!!! */
 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_HAS_ETH0
 #define CONFIG_ETHADDR  00:e0:0c:07:9b:8a
 #define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR  00:e0:0c:07:9b:8b