#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
/* Hardware drivers */
+/* GPIO support */
+#define CONFIG_OMAP_GPIO
+
+/* LED support */
+#define CONFIG_STATUS_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+#define CONFIG_CMD_LED /* LED command */
+#define STATUS_LED_BIT (1 << 0)
+#define STATUS_LED_STATE STATUS_LED_ON
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT1 (1 << 1)
+#define STATUS_LED_STATE1 STATUS_LED_ON
+#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT2 (1 << 2)
+#define STATUS_LED_STATE2 STATUS_LED_ON
+#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
+
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_DOS_PARTITION
/* I2C */
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
+
+
+/* EEPROM */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_BUS_NUM 1
/* TWL4030 */
#define CONFIG_TWL4030_POWER
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-#define CONFIG_NAND_OMAP_BCH8
#define CONFIG_BCH
+#define CONFIG_SYS_NAND_MAX_OOBFREE 2
+#define CONFIG_SYS_NAND_MAX_ECCPOS 56
/* commands to include */
#include <config_cmd_default.h>
/* Environment information (this is the common part) */
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 0
+
+/* hang() the board on panic() */
+#define CONFIG_PANIC_HANG
/* environment placement (for NAND), is different for FLASHCARD but does not
* harm there */
"vram=3M\0" \
"defaultdisplay=lcd\0" \
"kernelopts=mtdoops.mtddev=3\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
"commonargs=" \
"setenv bootargs console=${console} " \
"${mtdparts} " \
CONFIG_COMMON_ENV_SETTINGS \
CONFIG_ENV_RDADDR \
"autoboot=" \
- "mtdparts default; " \
"run commonargs; " \
"setenv bootargs ${bootargs} " \
"flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
- "loaduimage_ubi=mtd default; " \
- "ubi part ubi; " \
+ "loaduimage_ubi=ubi part ubi; " \
"ubifsmount ubi:root; " \
"ubifsload ${loadaddr} /boot/uImage\0" \
+ "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
- "run loaduimage_ubi; " \
+ "run loaduimage_nand; " \
"bootm ${loadaddr}\0" \
- "autoboot=mtdparts default;" \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
- 0x01000000) /* 16MB */
+ 0x07000000) /* 112 MB */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
*/
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
-#define CONFIG_SPL_MAX_SIZE (55 * 1024) /* 7 KB for stack */
+#define CONFIG_SPL_MAX_SIZE (57 * 1024) /* 7 KB for stack */
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
#define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 13
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000
#endif /* __CONFIG_H */