#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-#define CONFIG_NAND_DENALI_ECC_SIZE 1024
-
#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
-
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
/* SD/MMC */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "verify=n\0" \
"initrd_high=0xffffffffffffffff\0" \
"nor_base=0x42000000\0" \
"sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \
/* for LD20; the last 64 byte is used for dynamic DDR PHY training */
#define CONFIG_SYS_MEM_TOP_HIDE 64
-#define CONFIG_PANIC_HANG
-
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
/* only for SPL */