#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-#define CONFIG_NAND_DENALI_ECC_SIZE 1024
-
#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
-
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
/* SD/MMC */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_NR_DRAM_BANKS 3
-/* for LD20; the last 64 byte is used for dynamic DDR PHY training */
-#define CONFIG_SYS_MEM_TOP_HIDE 64
-
-#define CONFIG_PANIC_HANG
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
#define CONFIG_SPL_STACK (0x00100000)
-#define CONFIG_SPL_FRAMEWORK
-
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
/* subtract sizeof(struct image_header) */