]> git.sur5r.net Git - u-boot/blobdiff - include/configs/vpac270.h
PXA: Adapt Voipac PXA270 to OneNAND SPL
[u-boot] / include / configs / vpac270.h
index 1bcd2f3e049ec2a29be251431e391807df1767c0..8accebfce95fb74de43b521177543a2269524c2f 100644 (file)
  */
 #define        CONFIG_PXA27X           1       /* Marvell PXA270 CPU */
 #define        CONFIG_VPAC270          1       /* Voipac PXA270 board */
+#define        CONFIG_SYS_TEXT_BASE    0xa0000000
+
+#ifdef CONFIG_ONENAND
+#define        CONFIG_SPL
+#define        CONFIG_SPL_ONENAND_SUPPORT
+#define        CONFIG_SPL_ONENAND_LOAD_ADDR    0x2000
+#define        CONFIG_SPL_ONENAND_LOAD_SIZE    \
+       (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
+#define        CONFIG_SPL_TEXT_BASE    0x5c000000
+#define        CONFIG_SPL_LDSCRIPT     "board/vpac270/u-boot-spl.lds"
+#endif
 
 /*
  * Environment settings
  */
 #define        CONFIG_ENV_OVERWRITE
 #define        CONFIG_SYS_MALLOC_LEN           (128*1024)
-#define        CONFIG_SYS_GBL_DATA_SIZE        128
-
+#define        CONFIG_ARCH_CPU_INIT
 #define        CONFIG_BOOTCOMMAND                                              \
        "if mmc init && fatload mmc 0 0xa4000000 uImage; then "         \
                "bootm 0xa4000000; "                                    \
                "bootm 0xa4000000; "                                    \
        "fi; "                                                          \
        "bootm 0x60000;"
+
+#define        CONFIG_EXTRA_ENV_SETTINGS                                       \
+       "update_onenand="                                               \
+               "onenand erase 0x0 0x80000 ; "                          \
+               "onenand write 0xa0000000 0x0 0x80000"
+
 #define        CONFIG_BOOTARGS                 "console=tty0 console=ttyS0,115200"
 #define        CONFIG_TIMESTAMP
 #define        CONFIG_BOOTDELAY                2       /* Autoboot delay */
 #define        CONFIG_CMDLINE_TAG
 #define        CONFIG_SETUP_MEMORY_TAGS
-
 #define        CONFIG_LZMA                     /* LZMA compression support */
+#define        CONFIG_OF_LIBFDT
 
 /*
  * Serial Console Configuration
@@ -75,7 +91,7 @@
 #undef CONFIG_LCD
 #define        CONFIG_CMD_IDE
 
-#ifdef CONFIG_ONENAND_U_BOOT
+#ifdef CONFIG_ONENAND
 #undef CONFIG_CMD_FLASH
 #define        CONFIG_CMD_ONENAND
 #else
 #define        CONFIG_CMD_PING
 #define        CONFIG_CMD_DHCP
 
-#define        CONFIG_NET_MULTI                1
 #define        CONFIG_DRIVER_DM9000            1
 #define        CONFIG_DM9000_BASE              0x08000300      /* CS2 */
 #define        DM9000_IO                       (CONFIG_DM9000_BASE)
  */
 #ifdef CONFIG_CMD_MMC
 #define        CONFIG_MMC
-#define        CONFIG_PXA_MMC
+#define        CONFIG_GENERIC_MMC
+#define        CONFIG_PXA_MMC_GENERIC
 #define        CONFIG_SYS_MMC_BASE             0xF0000000
 #define        CONFIG_CMD_FAT
 #define        CONFIG_CMD_EXT2
 #define        PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
 #define        PHYS_SDRAM_1_SIZE               0x08000000      /* 128 MB */
 
-#ifdef CONFIG_256M_U_BOOT
+#ifdef CONFIG_RAM_256M
 #define        PHYS_SDRAM_2                    0x80000000      /* SDRAM Bank #2 */
 #define        PHYS_SDRAM_2_SIZE               0x08000000      /* 128 MB */
 #endif
 
 #define        CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
-#ifdef CONFIG_256M_U_BOOT
+#ifdef CONFIG_RAM_256M
 #define        CONFIG_SYS_DRAM_SIZE            0x10000000      /* 256 MB DRAM */
 #else
 #define        CONFIG_SYS_DRAM_SIZE            0x08000000      /* 128 MB DRAM */
 #define        CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
 #define        CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
 
-#define        CONFIG_SYS_LOAD_ADDR            (0x5c000000)
+#define        CONFIG_SYS_LOAD_ADDR            PHYS_SDRAM_1
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
-#define        CONFIG_SYS_INIT_SP_ADDR         \
-       (CONFIG_SYS_GBL_DATA_SIZE + CONFIG_STACKSIZE + PHYS_SDRAM_1)
+#define        CONFIG_SYS_INIT_SP_ADDR         0x5c010000
 
 /*
  * NOR FLASH
  */
 #define        CONFIG_SYS_MONITOR_BASE         0x0
-#define        CONFIG_SYS_MONITOR_LEN          0x40000
+#define        CONFIG_SYS_MONITOR_LEN          0x80000
 #define        CONFIG_ENV_ADDR                 \
                        (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 #define        CONFIG_ENV_SIZE                 0x4000
 #if    defined(CONFIG_CMD_FLASH)       /* NOR */
 #define        PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
 
-#ifdef CONFIG_256M_U_BOOT
+#ifdef CONFIG_RAM_256M
 #define        PHYS_FLASH_2                    0x02000000      /* Flash Bank #2 */
 #endif
 
 #define        CONFIG_FLASH_CFI_DRIVER         1
 
 #define        CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
-#ifdef CONFIG_256M_U_BOOT
+#ifdef CONFIG_RAM_256M
 #define        CONFIG_SYS_MAX_FLASH_BANKS      2
 #define        CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, PHYS_FLASH_2 }
 #else
 #define        CONFIG_SYS_MSC0_VAL     0x3ffc95fa
 #define        CONFIG_SYS_MSC1_VAL     0x02ccf974
 #define        CONFIG_SYS_MSC2_VAL     0x00000000
-#ifdef CONFIG_256M_U_BOOT
+#ifdef CONFIG_RAM_256M
 #define        CONFIG_SYS_MDCNFG_VAL   0x8ad30ad3
 #else
 #define        CONFIG_SYS_MDCNFG_VAL   0x88000ad3