+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration for Xilinx ZynqMP zcu102
*
* (C) Copyright 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_ZYNQMP_ZCU102_H
#define __CONFIG_ZYNQMP_ZCU102_H
#define CONFIG_ZYNQ_SDHCI1
-#define CONFIG_ZYNQ_I2C0
-#define CONFIG_ZYNQ_I2C1
#define CONFIG_SYS_I2C_MAX_HOPS 1
#define CONFIG_SYS_NUM_I2C_BUSES 18
#define CONFIG_SYS_I2C_BUSES { \
{1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \
}
-#define CONFIG_SYS_I2C_ZYNQ
#define CONFIG_PCA953X
-#define CONFIG_CMD_PCA953X_INFO
-
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_ZYNQ_EEPROM_BUS 5
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54
-#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0x20
+
+#define CONFIG_SPD_EEPROM
+#define CONFIG_DDR_SPD
#include <configs/xilinx_zynqmp.h>