]> git.sur5r.net Git - u-boot/blobdiff - include/dm/uclass-id.h
fdt_support: fdt_translate_address() blob const correctness
[u-boot] / include / dm / uclass-id.h
index 0777cbe27ee53676e72b0d095086693438bcd860..eb78c4dac485ac7a5bbe901b83b009ff827db278 100644 (file)
@@ -33,7 +33,6 @@ enum uclass_id {
        UCLASS_CROS_EC,         /* Chrome OS EC */
        UCLASS_DISPLAY,         /* Display (e.g. DisplayPort, HDMI) */
        UCLASS_DMA,             /* Direct Memory Access */
-       UCLASS_RAM,             /* RAM controller */
        UCLASS_ETH,             /* Ethernet device */
        UCLASS_GPIO,            /* Bank of general-purpose I/O pins */
        UCLASS_I2C,             /* I2C bus */
@@ -56,13 +55,16 @@ enum uclass_id {
        UCLASS_PCH,             /* x86 platform controller hub */
        UCLASS_PCI,             /* PCI bus */
        UCLASS_PCI_GENERIC,     /* Generic PCI bus device */
-       UCLASS_PINCTRL,         /* Pinctrl (pin muxing/configuration) device */
        UCLASS_PINCONFIG,       /* Pin configuration node device */
+       UCLASS_PINCTRL,         /* Pinctrl (pin muxing/configuration) device */
        UCLASS_PMIC,            /* PMIC I/O device */
        UCLASS_PWM,             /* Pulse-width modulator */
+       UCLASS_POWER_DOMAIN,    /* (SoC) Power domains */
        UCLASS_PWRSEQ,          /* Power sequence device */
+       UCLASS_RAM,             /* RAM controller */
        UCLASS_REGULATOR,       /* Regulator device */
        UCLASS_REMOTEPROC,      /* Remote Processor device */
+       UCLASS_RESET,           /* Reset controller device */
        UCLASS_RTC,             /* Real time clock device */
        UCLASS_SERIAL,          /* Serial UART */
        UCLASS_SPI,             /* SPI bus */