/* Status Register */
#define DWMCI_BUSY (1 << 9)
+#define DWMCI_FIFO_MASK 0x1ff
+#define DWMCI_FIFO_SHIFT 17
/* FIFOTH Register */
#define MSIZE(x) ((x) << 28)
#define DWMCI_BMOD_IDMAC_FB (1 << 1)
#define DWMCI_BMOD_IDMAC_EN (1 << 7)
+/* UHS register */
+#define DWMCI_DDR_MODE (1 << 16)
+
/* quirks */
#define DWMCI_QUIRK_DISABLE_SMU (1 << 0)
+/**
+ * struct dwmci_host - Information about a designware MMC host
+ *
+ * @name: Device name
+ * @ioaddr: Base I/O address of controller
+ * @quirks: Quick flags - see DWMCI_QUIRK_...
+ * @caps: Capabilities - see MMC_MODE_...
+ * @bus_hz: Bus speed in Hz, if @get_mmc_clk() is NULL
+ * @div: Arbitrary clock divider value for use by controller
+ * @dev_index: Arbitrary device index for use by controller
+ * @dev_id: Arbitrary device ID for use by controller
+ * @buswidth: Bus width in bits (8 or 4)
+ * @fifoth_val: Value for FIFOTH register (or 0 to leave unset)
+ * @mmc: Pointer to generic MMC structure for this device
+ * @priv: Private pointer for use by controller
+ */
struct dwmci_host {
- char *name;
+ const char *name;
void *ioaddr;
unsigned int quirks;
unsigned int caps;
unsigned int version;
unsigned int clock;
unsigned int bus_hz;
+ unsigned int div;
int dev_index;
+ int dev_id;
int buswidth;
- u32 clksel_val;
u32 fifoth_val;
struct mmc *mmc;
+ void *priv;
void (*clksel)(struct dwmci_host *host);
- unsigned int (*get_mmc_clk)(int dev_index);
+ void (*board_init)(struct dwmci_host *host);
+
+ /**
+ * Get / set a particular MMC clock frequency
+ *
+ * This is used to request the current clock frequency of the clock
+ * that drives the DWMMC peripheral. The caller will then use this
+ * information to work out the divider it needs to achieve the
+ * required MMC bus clock frequency. If you want to handle the
+ * clock external to DWMMC, use @freq to select the frequency and
+ * return that value too. Then DWMMC will put itself in bypass mode.
+ *
+ * @host: DWMMC host
+ * @freq: Frequency the host is trying to achieve
+ */
+ unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
+#ifndef CONFIG_BLK
+ struct mmc_config cfg;
+#endif
+
+ /* use fifo mode to read and write data */
+ bool fifo_mode;
};
struct dwmci_idmac {
u32 cnt;
u32 addr;
u32 next_addr;
-};
+} __aligned(ARCH_DMA_MINALIGN);
static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
{
return readb(host->ioaddr + reg);
}
+void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
+ uint caps, u32 max_clk, u32 min_clk);
+int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
+
int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
#endif /* __DWMMC_HW_H */