Enable dual DDR controllers and interleaving.

[u-boot] / include / e500.h

diff --git a/include/e500.h b/include/e500.h
index 5489ba2fe3214e7fe717eb7b6cc3d862b4d7a3f3..8e3bf8cb7d25a44126721dd94d3eac4d5dcf4277 100644 (file)
--- a/include/e500.h
+++ b/include/e500.h
@@ -20,14 +20,29 @@ typedef struct
  * initial memory mapping like legacy BAT registers do. Usually we
  * use four MAS registers(MAS0-3) to operate on TLB1 entries.
  *
+ * While there are 16 Entries with variable Page Sizes in TLB1,
+ * there are also 256 Entries with fixed 4K pages in TLB0.
+ *
  * We also need LAWs(Local Access Window) to associate a range of
  * the local 32-bit address space with a particular target interface
  * such as PCI/PCI-X, RapidIO, Local Bus and DDR SDRAM.
  *
  * We put TLB1/LAW code here because memory mapping is board-specific
  * instead of cpu-specific.
+ *
+ * While these macros are all nominally for TLB1 by name, they can
+ * also be used for TLB0 as well.
  */
 
+
+/*
+ * Convert addresses to Effective and Real Page Numbers.
+ * Grab the high 20-bits and shift 'em down, dropping the "byte offset".
+ */
+#define E500_TLB_EPN(addr)     (((addr) >> 12) & 0xfffff)
+#define E500_TLB_RPN(addr)     (((addr) >> 12) & 0xfffff)
+
+
 /* MAS0
  * tlbsel(TLB Select):0,1
  * esel(Entry Select): 0,1,2,...,15 for TLB1