ARM: zynq: Remove ZYNQ_BOOT_FREEBSD option

[u-boot] / include / fdtdec.h

diff --git a/include/fdtdec.h b/include/fdtdec.h
index 25e98c9c9e1ae2e3f0c73fd069c05374e8f54c3d..4caf3b6cbda229f71a8a222d9691fee5c8e4bd78 100644 (file)
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -120,7 +120,6 @@ enum fdt_compat_id {
        COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
        COMPAT_NVIDIA_TEGRA20_NAND,     /* Tegra2 NAND controller */
        COMPAT_NVIDIA_TEGRA20_PWM,      /* Tegra 2 PWM controller */
-       COMPAT_NVIDIA_TEGRA124_DC,      /* Tegra 124 Display controller */
        COMPAT_NVIDIA_TEGRA124_SOR,     /* Tegra 124 Serial Output Resource */
        COMPAT_NVIDIA_TEGRA124_PMC,     /* Tegra 124 power mgmt controller */
        COMPAT_NVIDIA_TEGRA20_DC,       /* Tegra 2 Display controller */
@@ -163,7 +162,6 @@ enum fdt_compat_id {
        COMPAT_INTEL_X86_PINCTRL,       /* Intel ICH7/9 pin control */
        COMPAT_SOCIONEXT_XHCI,          /* Socionext UniPhier xHCI */
        COMPAT_INTEL_PCH,               /* Intel PCH */
-       COMPAT_INTEL_IRQ_ROUTER,        /* Intel Interrupt Router */
        COMPAT_ALTERA_SOCFPGA_DWMAC,    /* SoCFPGA Ethernet controller */
        COMPAT_ALTERA_SOCFPGA_DWMMC,    /* SoCFPGA DWMMC controller */
        COMPAT_ALTERA_SOCFPGA_DWC2USB,  /* SoCFPGA DWC2 USB controller */
@@ -723,6 +721,15 @@ const u32 *fdtdec_locate_array(const void *blob, int node,
  */
 int fdtdec_get_bool(const void *blob, int node, const char *prop_name);
 
+/*
+ * Count child nodes of one parent node.
+ *
+ * @param blob FDT blob
+ * @param node parent node
+ * @return number of child node; 0 if there is not child node
+ */
+int fdtdec_get_child_count(const void *blob, int node);
+
 /**
  * Look in the FDT for a config item with the given name and return its value
  * as a 32-bit integer. The property must have at least 4 bytes of data. The