+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2008-2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0
*/
#ifndef DDR2_DIMM_PARAMS_H
unsigned int n_banks_per_sdram_device;
#endif
unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
- unsigned int row_density;
/* used in computing base address of DIMMs */
unsigned long long base_address;
int tqhs_ps; /* byte 45, spd->tqhs */
#endif
- /* DDR3 RDIMM */
+ /* DDR3 & DDR4 RDIMM */
unsigned char rcw[16]; /* Register Control Word 0-15 */
#ifdef CONFIG_SYS_FSL_DDR4
unsigned int dq_mapping[18];