+/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright 2008-2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0
+ * Copyright 2008-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP Semiconductor
*/
#ifndef DDR2_DIMM_PARAMS_H
char mpart[19]; /* guaranteed null terminated */
unsigned int n_ranks;
+ unsigned int die_density;
unsigned long long rank_density;
unsigned long long capacity;
unsigned int data_width;
unsigned int primary_sdram_width;
unsigned int ec_sdram_width;
unsigned int registered_dimm;
+ unsigned int package_3ds; /* number of dies in 3DS DIMM */
unsigned int device_width; /* x4, x8, x16 components */
/* SDRAM device parameters */
unsigned int n_banks_per_sdram_device;
#endif
unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
- unsigned int row_density;
/* used in computing base address of DIMMs */
unsigned long long base_address;
int trrds_ps;
int trrdl_ps;
int tccdl_ps;
+ int trfc_slr_ps;
#else
int twr_ps; /* maximum = 63750 ps */
int trfc_ps; /* max = 255 ns + 256 ns + .75 ns
int tqhs_ps; /* byte 45, spd->tqhs */
#endif
- /* DDR3 RDIMM */
+ /* DDR3 & DDR4 RDIMM */
unsigned char rcw[16]; /* Register Control Word 0-15 */
#ifdef CONFIG_SYS_FSL_DDR4
unsigned int dq_mapping[18];