arm: am57xx: cl-som-am57x: add ETH support

[u-boot] / include / fsl_ddr_sdram.h

diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index acddf14a3f5f6affa8e8f82b3256e531d366e49b..1404c5793607089c519c8d8f6dfe0fc9ef18fe57 100644 (file)
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -189,6 +189,10 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define DDR_MR5_CA_PARITY_LAT_4_CLK    0x1 /* for DDR4-1600/1866/2133 */
 #define DDR_MR5_CA_PARITY_LAT_5_CLK    0x2 /* for DDR4-2400 */
 
+/* DEBUG_26 register */
+#define DDR_CAS_TO_PRE_SUB_MASK  0x0000f000 /* CAS to preamble subtract value */
+#define DDR_CAS_TO_PRE_SUB_SHIFT 12
+
 /* DEBUG_29 register */
 #define DDR_TX_BD_DIS  (1 << 10) /* Transmit Bit Deskew Disable */
 
@@ -295,7 +299,7 @@ typedef struct fsl_ddr_cfg_regs_s {
        unsigned int ddr_cdr2;
        unsigned int err_disable;
        unsigned int err_int_en;
-       unsigned int debug[32];
+       unsigned int debug[64];
 } fsl_ddr_cfg_regs_t;
 
 typedef struct memctl_options_partial_s {
@@ -370,7 +374,8 @@ typedef struct memctl_options_s {
        unsigned int additive_latency_override_value;
 
        unsigned int clk_adjust;                /* */
-       unsigned int cpo_override;
+       unsigned int cpo_override;              /* override timing_cfg_2[CPO]*/
+       unsigned int cpo_sample;                /* optimize debug_29[24:31] */
        unsigned int write_data_delay;          /* DQS adjust */
 
        unsigned int cswl_override;