#define DDR_DATA_BUS_WIDTH_64 0
#define DDR_DATA_BUS_WIDTH_32 1
#define DDR_DATA_BUS_WIDTH_16 2
+#define DDR_CSWL_CS0 0x04000001
/*
* Generalized parameters for memory controller configuration,
* might be a little specific to the FSL memory controller
unsigned int cpo_override;
unsigned int write_data_delay; /* DQS adjust */
+ unsigned int cswl_override;
unsigned int wrlvl_override;
unsigned int wrlvl_sample; /* Write leveling */
unsigned int wrlvl_start;
int board_need_mem_reset(void)
__attribute__((weak, alias("__board_need_mem_reset")));
+void __weak board_mem_sleep_setup(void)
+{
+}
+
/*
* The 85xx boards have a common prototype for fixed_sdram so put the
* declaration here.