u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */
u8 res_258[0x260-0x258];
u32 sdram_cfg_3;
- u8 res_264[0x2a0-0x264];
- u32 deskew_cntl;
- u8 res_2a4[0x400-0x2a4];
+ u8 res_264[0x400-0x264];
u32 dq_map_0;
u32 dq_map_1;
u32 dq_map_2;
u32 capture_ext_address; /* Error Extended Addr Capture */
u32 err_sbe; /* Single-Bit ECC Error Management */
u8 res_e5c[164];
- u32 debug[32]; /* debug_1 to debug_32 */
- u8 res_f80[128];
+ u32 debug[64]; /* debug_1 to debug_64 */
};
#endif /* __FSL_IMMAP_H */