SPDX: Convert all of our single license tags to Linux Kernel style

[u-boot] / include / linux / usb / dwc3.h

diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
index 97d179a6e9e747ab657c4025796bfeb047f3a0bb..9ceee0a1c9f6eb61dd349a725a89276959c73747 100644 (file)
--- a/include/linux/usb/dwc3.h
+++ b/include/linux/usb/dwc3.h
@@ -1,10 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /* include/linux/usb/dwc3.h
  *
  * Copyright (c) 2012 Samsung Electronics Co. Ltd
  *
  * Designware SuperSpeed USB 3.0 DRD Controller global and OTG registers
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __DWC3_H_
@@ -41,7 +40,8 @@
 #define DWC3_REG_OFFSET                                0xC100
 
 struct g_event_buffer {
-       u64 g_evntadr;
+       u32 g_evntadrlo;
+       u32 g_evntadrhi;
        u32 g_evntsiz;
        u32 g_evntcount;
 };
@@ -108,7 +108,11 @@ struct dwc3 {                                      /* offset: 0xC100 */
 
        u32 g_hwparams8;
 
-       u32 reserved4[63];
+       u32 reserved4[11];
+
+       u32 g_fladj;
+
+       u32 reserved5[51];
 
        u32 d_cfg;
        u32 d_ctl;
@@ -117,15 +121,15 @@ struct dwc3 {                                     /* offset: 0xC100 */
        u32 d_gcmdpar;
        u32 d_gcmd;
 
-       u32 reserved5[2];
+       u32 reserved6[2];
 
        u32 d_alepena;
 
-       u32 reserved6[55];
+       u32 reserved7[55];
 
        struct d_physical_endpoint d_phy_ep_cmd[32];
 
-       u32 reserved7[128];
+       u32 reserved8[128];
 
        u32 o_cfg;
        u32 o_ctl;
@@ -133,7 +137,7 @@ struct dwc3 {                                       /* offset: 0xC100 */
        u32 o_evten;
        u32 o_sts;
 
-       u32 reserved8[3];
+       u32 reserved9[3];
 
        u32 adp_cfg;
        u32 adp_ctl;
@@ -142,7 +146,7 @@ struct dwc3 {                                       /* offset: 0xC100 */
 
        u32 bc_cfg;
 
-       u32 reserved9;
+       u32 reserved10;
 
        u32 bc_evt;
        u32 bc_evten;
@@ -175,14 +179,45 @@ struct dwc3 {                                     /* offset: 0xC100 */
 
 /* Global USB2 PHY Configuration Register */
 #define DWC3_GUSB2PHYCFG_PHYSOFTRST            (1 << 31)
+#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS     (1 << 30)
+#define DWC3_GUSB2PHYCFG_ENBLSLPM              (1 << 8)
 #define DWC3_GUSB2PHYCFG_SUSPHY                        (1 << 6)
+#define DWC3_GUSB2PHYCFG_PHYIF                 (1 << 3)
+
+/* Global USB2 PHY Configuration Mask */
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK                (0xf << 10)
+
+/* Global USB2 PHY Configuration Offset */
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET      10
+
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \
+               DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \
+               DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
 
 /* Global USB3 PIPE Control Register */
 #define DWC3_GUSB3PIPECTL_PHYSOFTRST           (1 << 31)
+#define DWC3_GUSB3PIPECTL_DISRXDETP3           (1 << 28)
 #define DWC3_GUSB3PIPECTL_SUSPHY               (1 << 17)
 
 /* Global TX Fifo Size Register */
 #define DWC3_GTXFIFOSIZ_TXFDEF(n)              ((n) & 0xffff)
 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n)           ((n) & 0xffff0000)
 
+/* Device Control Register */
+#define DWC3_DCTL_RUN_STOP                     (1 << 31)
+#define DWC3_DCTL_CSFTRST                      (1 << 30)
+#define DWC3_DCTL_LSFTRST                      (1 << 29)
+
+/* Global Frame Length Adjustment Register */
+#define GFLADJ_30MHZ_REG_SEL                   (1 << 7)
+#define GFLADJ_30MHZ(n)                                ((n) & 0x3f)
+#define GFLADJ_30MHZ_DEFAULT                   0x20
+
+#ifdef CONFIG_USB_XHCI_DWC3
+void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
+void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
+int dwc3_core_init(struct dwc3 *dwc3_reg);
+void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val);
+#endif
 #endif /* __DWC3_H_ */