/* General Purpose Timers registers */
#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
+#define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10)
+#define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14)
+#define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20)
+#define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24)
+#define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30)
+#define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34)
+#define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40)
+#define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44)
+#define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50)
+#define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54)
+#define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60)
+#define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64)
+#define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70)
+#define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74)
+
+#define MPC5XXX_GPT7_PWMCFG (MPC5XXX_GPT + 0x78)
/* ATA registers */
#define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000)