[PATCH v3] Add sync to ensure flash_write_cmd is fully finished

[u-boot] / include / mpc8260.h

diff --git a/include/mpc8260.h b/include/mpc8260.h
index 1b67c2b9776f6457e6e8d2dd07bc6ab24b8883ae..d9dd92d9a5e876b5ef0dc6f2d3ad68a4edd1ebc2 100644 (file)
--- a/include/mpc8260.h
+++ b/include/mpc8260.h
@@ -34,8 +34,20 @@
 #define CPU_ID_STR     "MPC8255"
 #endif
 #ifndef CPU_ID_STR
+#if defined(CONFIG_MPC8272_FAMILY)
+#ifdef CONFIG_MPC8247
+#define CPU_ID_STR     "MPC8247"
+#elif defined CONFIG_MPC8248
+#define CPU_ID_STR     "MPC8248"
+#elif defined CONFIG_MPC8271
+#define CPU_ID_STR     "MPC8271"
+#else
+#define CPU_ID_STR     "MPC8272"
+#endif
+#else
 #define CPU_ID_STR     "MPC8260"
 #endif
+#endif /* !CPU_ID_STR */
 
 /*-----------------------------------------------------------------------
  * Exception offsets (PowerPC standard)
@@ -62,6 +74,7 @@
 #define BCR_EXDD       0x00000400      /* External Master Delay Disable*/
 #define BCR_ISPS       0x00000010      /* Internal Space Port Size     */
 
+
 /*-----------------------------------------------------------------------
  * PPC_ACR - 60x Bus Arbiter Configuration Register                     4-28
  */
@@ -164,6 +177,7 @@
 #define SIUMCR_MMR10   0x00008000      /* - " -                        */
 #define SIUMCR_MMR11   0x0000c000      /* - " -                        */
 #define SIUMCR_LPBSE   0x00002000      /* LocalBus Parity Byte Select Enable*/
+#define SIUMCR_ABE     0x00000400      /* Address output buffer impedance*/
 
 /*-----------------------------------------------------------------------
  * IMMR - Internal Memory Map Register                                  4-34
@@ -288,6 +302,10 @@
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control Register                                         9-8
  */
+#define SCCR_PCI_MODE  0x00000100      /* PCI Mode     */
+#define SCCR_PCI_MODCK 0x00000080      /* Value of PCI_MODCK pin       */
+#define SCCR_PCIDF_MSK 0x00000078      /* PCI division factor  */
+#define SCCR_PCIDF_SHIFT 3
 #define SCCR_CLPD      0x00000004      /* CPM Low Power Disable        */
 #define SCCR_DFBRG_MSK 0x00000003      /* Division factor of BRGCLK Mask */
 #define SCCR_DFBRG_SHIFT 0
@@ -300,14 +318,15 @@
 /*-----------------------------------------------------------------------
  * SCMR - System Clock Mode Register                                    9-9
  */
-#define SCMR_CORECNF_MSK 0x1f000000    /* Core Configuration Mask      */
+#define SCMR_CORECNF_MSK   0x1f000000  /* Core Configuration Mask      */
 #define SCMR_CORECNF_SHIFT 24
-#define SCMR_BUSDF_MSK 0x00f00000      /* 60x Bus Division Factor Mask */
-#define SCMR_BUSDF_SHIFT 20
-#define SCMR_CPMDF_MSK 0x000f0000      /* CPM Division Factor Mask     */
-#define SCMR_CPMDF_SHIFT 16
-#define SCMR_PLLDF     0x00001000      /* PLL Pre-divider Value        */
-#define SCMR_PLLMF_MSK 0x00000fff      /* PLL Multiplication Factor Mask*/
+#define SCMR_BUSDF_MSK    0x00f00000   /* 60x Bus Division Factor Mask */
+#define SCMR_BUSDF_SHIFT   20
+#define SCMR_CPMDF_MSK    0x000f0000   /* CPM Division Factor Mask     */
+#define SCMR_CPMDF_SHIFT   16
+#define SCMR_PLLDF        0x00001000   /* PLL Pre-divider Value        */
+#define SCMR_PLLMF_MSK    0x00000fff   /* PLL Multiplication Factor Mask*/
+#define SCMR_PLLMF_MSKH7   0x0000000f  /* for HiP7 processors */
 #define SCMR_PLLMF_SHIFT 0