Support for the MX31ADS evaluation board from Freescale

[u-boot] / include / mpc83xx.h

diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 7299ca00bc41d962b4879aaa25a3c4e63f11c537..4ee38aafa94f0dfc988ee77ed21c5f769c686011 100644 (file)
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -121,6 +121,7 @@
 #define SPCR_PCIPR                     0x03000000      /* PCI bridge system bus request priority */
 #define SPCR_PCIPR_SHIFT               (31-7)
 #define SPCR_OPT                       0x00800000      /* Optimize */
+#define SPCR_OPT_SHIFT                 (31-8)
 #define SPCR_TBEN                      0x00400000      /* E300 PowerPC core time base unit enable */
 #define SPCR_TBEN_SHIFT                        (31-9)
 #define SPCR_COREPR                    0x00300000      /* E300 PowerPC Core system bus request priority */
@@ -728,6 +729,7 @@
 /* TSEC1 bits are for TSEC2 as well */
 #define SCCR_TSEC1CM                   0xc0000000
 #define SCCR_TSEC1CM_SHIFT             30
+#define SCCR_TSEC1CM_0                 0x00000000
 #define SCCR_TSEC1CM_1                 0x40000000
 #define SCCR_TSEC1CM_2                 0x80000000
 #define SCCR_TSEC1CM_3                 0xC0000000
@@ -852,6 +854,7 @@
  */
 #define CSCONFIG_EN                    0x80000000
 #define CSCONFIG_AP                    0x00800000
+#define CSCONFIG_ODT_WR_ACS            0x00010000
 #define CSCONFIG_ROW_BIT               0x00000700
 #define CSCONFIG_ROW_BIT_12            0x00000000
 #define CSCONFIG_ROW_BIT_13            0x00000100
@@ -878,7 +881,7 @@
 #define TIMING_CFG0_PRE_PD_EXIT_SHIFT  16
 #define TIMING_CFG0_ODT_PD_EXIT                0x00000F00
 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT  8
-#define TIMING_CFG0_MRS_CYC            0x00000F00
+#define TIMING_CFG0_MRS_CYC            0x0000000F
 #define TIMING_CFG0_MRS_CYC_SHIFT      0
 
 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
@@ -901,6 +904,7 @@
 #define TIMING_CFG1_WRTORD_SHIFT       0
 #define TIMING_CFG1_CASLAT_20          0x00030000      /* CAS latency = 2.0 */
 #define TIMING_CFG1_CASLAT_25          0x00040000      /* CAS latency = 2.5 */
+#define TIMING_CFG1_CASLAT_30          0x00050000      /* CAS latency = 2.5 */
 
 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
  */
@@ -1480,6 +1484,7 @@
 
 /* DDRCDR - DDR Control Driver Register
  */
+#define DDRCDR_DHC_EN          0x80000000
 #define DDRCDR_EN              0x40000000
 #define DDRCDR_PZ              0x3C000000
 #define DDRCDR_PZ_MAXZ         0x00000000