Support for the MX31ADS evaluation board from Freescale

[u-boot] / include / mpc83xx.h

diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index dba1aea4fa98ffd70c160d7857a953a25212edaa..4ee38aafa94f0dfc988ee77ed21c5f769c686011 100644 (file)
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -121,6 +121,7 @@
 #define SPCR_PCIPR                     0x03000000      /* PCI bridge system bus request priority */
 #define SPCR_PCIPR_SHIFT               (31-7)
 #define SPCR_OPT                       0x00800000      /* Optimize */
+#define SPCR_OPT_SHIFT                 (31-8)
 #define SPCR_TBEN                      0x00400000      /* E300 PowerPC core time base unit enable */
 #define SPCR_TBEN_SHIFT                        (31-9)
 #define SPCR_COREPR                    0x00300000      /* E300 PowerPC Core system bus request priority */
@@ -145,10 +146,10 @@
 /* SPCR bits - MPC831x and MPC837x specific */
 #define SPCR_TSECDP                    0x00003000      /* TSEC data priority */
 #define SPCR_TSECDP_SHIFT              (31-19)
-#define SPCR_TSECEP                    0x00000C00      /* TSEC emergency priority */
-#define SPCR_TSECEP_SHIFT              (31-21)
-#define SPCR_TSECBDP                   0x00000300      /* TSEC buffer descriptor priority */
-#define SPCR_TSECBDP_SHIFT             (31-23)
+#define SPCR_TSECBDP                   0x00000C00      /* TSEC buffer descriptor priority */
+#define SPCR_TSECBDP_SHIFT             (31-21)
+#define SPCR_TSECEP                    0x00000300      /* TSEC emergency priority */
+#define SPCR_TSECEP_SHIFT              (31-23)
 #endif
 
 /* SICRL/H - System I/O Configuration Register Low/High
@@ -486,7 +487,15 @@
 #define HRCWL_CE_TO_PLL_1X30           0x0000001E
 #define HRCWL_CE_TO_PLL_1X31           0x0000001F
 
-#elif defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
+#elif defined(CONFIG_MPC8315)
+#define HRCWL_SVCOD                    0x30000000
+#define HRCWL_SVCOD_SHIFT              28
+#define HRCWL_SVCOD_DIV_2              0x00000000
+#define HRCWL_SVCOD_DIV_4              0x10000000
+#define HRCWL_SVCOD_DIV_8              0x20000000
+#define HRCWL_SVCOD_DIV_1              0x30000000
+
+#elif defined(CONFIG_MPC837X)
 #define HRCWL_SVCOD                    0x30000000
 #define HRCWL_SVCOD_SHIFT              28
 #define HRCWL_SVCOD_DIV_4              0x00000000
@@ -720,6 +729,7 @@
 /* TSEC1 bits are for TSEC2 as well */
 #define SCCR_TSEC1CM                   0xc0000000
 #define SCCR_TSEC1CM_SHIFT             30
+#define SCCR_TSEC1CM_0                 0x00000000
 #define SCCR_TSEC1CM_1                 0x40000000
 #define SCCR_TSEC1CM_2                 0x80000000
 #define SCCR_TSEC1CM_3                 0xC0000000
@@ -752,31 +762,31 @@
 #define SCCR_TSEC2CM_2                 0x20000000
 #define SCCR_TSEC2CM_3                 0x30000000
 
-#define SCCR_USBDRCM                   0x00300000
-#define SCCR_USBDRCM_SHIFT             20
+#define SCCR_USBDRCM                   0x00c00000
+#define SCCR_USBDRCM_SHIFT             22
 #define SCCR_USBDRCM_0                 0x00000000
-#define SCCR_USBDRCM_1                 0x00100000
-#define SCCR_USBDRCM_2                 0x00200000
-#define SCCR_USBDRCM_3                 0x00300000
+#define SCCR_USBDRCM_1                 0x00400000
+#define SCCR_USBDRCM_2                 0x00800000
+#define SCCR_USBDRCM_3                 0x00c00000
 
-#define SCCR_PCIEXP1CM                 0x00080000
-#define SCCR_PCIEXP2CM                 0x00040000
+#define SCCR_PCIEXP1CM                 0x00300000
+#define SCCR_PCIEXP2CM                 0x000c0000
 
-#define SCCR_SATA1CM                   0x0000c000
-#define SCCR_SATA1CM_SHIFT             14
-#define SCCR_SATACM                    0x0000f000
-#define SCCR_SATACM_SHIFT              8
+#define SCCR_SATA1CM                   0x00003000
+#define SCCR_SATA1CM_SHIFT             12
+#define SCCR_SATACM                    0x00003c00
+#define SCCR_SATACM_SHIFT              10
 #define SCCR_SATACM_0                  0x00000000
-#define SCCR_SATACM_1                  0x00005000
-#define SCCR_SATACM_2                  0x0000a000
-#define SCCR_SATACM_3                  0x0000f000
+#define SCCR_SATACM_1                  0x00001400
+#define SCCR_SATACM_2                  0x00002800
+#define SCCR_SATACM_3                  0x00003c00
 
-#define SCCR_TDMCM                     0x000000c0
-#define SCCR_TDMCM_SHIFT               6
+#define SCCR_TDMCM                     0x00000030
+#define SCCR_TDMCM_SHIFT               4
 #define SCCR_TDMCM_0                   0x00000000
-#define SCCR_TDMCM_1                   0x00000040
-#define SCCR_TDMCM_2                   0x00000080
-#define SCCR_TDMCM_3                   0x000000c0
+#define SCCR_TDMCM_1                   0x00000010
+#define SCCR_TDMCM_2                   0x00000020
+#define SCCR_TDMCM_3                   0x00000030
 
 #elif defined(CONFIG_MPC837X)
 /* SCCR bits - MPC837x specific */
@@ -844,6 +854,7 @@
  */
 #define CSCONFIG_EN                    0x80000000
 #define CSCONFIG_AP                    0x00800000
+#define CSCONFIG_ODT_WR_ACS            0x00010000
 #define CSCONFIG_ROW_BIT               0x00000700
 #define CSCONFIG_ROW_BIT_12            0x00000000
 #define CSCONFIG_ROW_BIT_13            0x00000100
@@ -870,7 +881,7 @@
 #define TIMING_CFG0_PRE_PD_EXIT_SHIFT  16
 #define TIMING_CFG0_ODT_PD_EXIT                0x00000F00
 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT  8
-#define TIMING_CFG0_MRS_CYC            0x00000F00
+#define TIMING_CFG0_MRS_CYC            0x0000000F
 #define TIMING_CFG0_MRS_CYC_SHIFT      0
 
 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
@@ -893,6 +904,7 @@
 #define TIMING_CFG1_WRTORD_SHIFT       0
 #define TIMING_CFG1_CASLAT_20          0x00030000      /* CAS latency = 2.0 */
 #define TIMING_CFG1_CASLAT_25          0x00040000      /* CAS latency = 2.5 */
+#define TIMING_CFG1_CASLAT_30          0x00050000      /* CAS latency = 2.5 */
 
 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
  */
@@ -1472,6 +1484,7 @@
 
 /* DDRCDR - DDR Control Driver Register
  */
+#define DDRCDR_DHC_EN          0x80000000
 #define DDRCDR_EN              0x40000000
 #define DDRCDR_PZ              0x3C000000
 #define DDRCDR_PZ_MAXZ         0x00000000