Merge with /home/wd/git/u-boot/custodian/u-boot-mpc86xx

[u-boot] / include / mpc83xx.h

diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 1b62f8129383f058ce79a9c29a4d16c344995230..c2a4ff587745d69bb9bedd394b58726f38a6c322 100644 (file)
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -68,12 +68,23 @@
 #define SPR_8343E_REV11                        0x80360101
 #define SPR_8343_REV11                 0x80370101
 
+#define SPR_8349E_REV31                        0x80300300
+#define SPR_8349_REV31                 0x80310300
+#define SPR_8347E_REV31_TBGA           0x80320300
+#define SPR_8347_REV31_TBGA            0x80330300
+#define SPR_8347E_REV31_PBGA           0x80340300
+#define SPR_8347_REV31_PBGA            0x80350300
+#define SPR_8343E_REV31                        0x80360300
+#define SPR_8343_REV31                 0x80370300
+
 #define SPR_8360E_REV10                        0x80480010
 #define SPR_8360_REV10                 0x80490010
 #define SPR_8360E_REV11                        0x80480011
 #define SPR_8360_REV11                 0x80490011
 #define SPR_8360E_REV12                        0x80480012
 #define SPR_8360_REV12                 0x80490012
+#define SPR_8360E_REV20                        0x80480020
+#define SPR_8360_REV20                 0x80490020
 
 #define SPR_8323E_REV10                        0x80620010
 #define SPR_8323_REV10                 0x80630010
@@ -498,6 +509,7 @@
 #define SCCR_PCICM_SHIFT               16
 
 /* SCCR bits - MPC8349 specific */
+#ifdef CONFIG_MPC834X
 #define SCCR_TSEC1CM                   0xc0000000
 #define SCCR_TSEC1CM_SHIFT             30
 #define SCCR_TSEC1CM_0                 0x00000000
@@ -511,6 +523,7 @@
 #define SCCR_TSEC2CM_1                 0x10000000
 #define SCCR_TSEC2CM_2                 0x20000000
 #define SCCR_TSEC2CM_3                 0x30000000
+#endif
 
 #define SCCR_USBMPHCM                  0x00c00000
 #define SCCR_USBMPHCM_SHIFT            22
@@ -522,13 +535,6 @@
 #define SCCR_USBCM_2                   0x00A00000
 #define SCCR_USBCM_3                   0x00F00000
 
-#define SCCR_CLK_MASK                  ( SCCR_TSEC1CM_3        \
-                                       | SCCR_TSEC2CM_3        \
-                                       | SCCR_ENCCM_3          \
-                                       | SCCR_USBCM_3          )
-
-#define SCCR_DEFAULT                   0xFFFFFFFF
-
 /* CSn_BDNS - Chip Select memory Bounds Register
  */
 #define CSBNDS_SA                      0x00FF0000
@@ -573,8 +579,8 @@
 
 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
  */
-#define TIMING_CFG2_CPO                        0x0F000000
-#define TIMING_CFG2_CPO_SHIFT          24
+#define TIMING_CFG2_CPO                        0x0F800000
+#define TIMING_CFG2_CPO_SHIFT          23
 #define TIMING_CFG2_ACSM               0x00080000
 #define TIMING_CFG2_WR_DATA_DELAY      0x00001C00
 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT        10