]> git.sur5r.net Git - u-boot/blobdiff - include/mpc83xx.h
Coding Style Cleanup, new CHANGELOG
[u-boot] / include / mpc83xx.h
index 73f2721619379caeef7d46d3abd533d560426810..c2a4ff587745d69bb9bedd394b58726f38a6c322 100644 (file)
@@ -83,6 +83,8 @@
 #define SPR_8360_REV11                 0x80490011
 #define SPR_8360E_REV12                        0x80480012
 #define SPR_8360_REV12                 0x80490012
+#define SPR_8360E_REV20                        0x80480020
+#define SPR_8360_REV20                 0x80490020
 
 #define SPR_8323E_REV10                        0x80620010
 #define SPR_8323_REV10                 0x80630010
 #define SCCR_PCICM_SHIFT               16
 
 /* SCCR bits - MPC8349 specific */
+#ifdef CONFIG_MPC834X
 #define SCCR_TSEC1CM                   0xc0000000
 #define SCCR_TSEC1CM_SHIFT             30
 #define SCCR_TSEC1CM_0                 0x00000000
 #define SCCR_TSEC2CM_1                 0x10000000
 #define SCCR_TSEC2CM_2                 0x20000000
 #define SCCR_TSEC2CM_3                 0x30000000
+#endif
 
 #define SCCR_USBMPHCM                  0x00c00000
 #define SCCR_USBMPHCM_SHIFT            22
 #define SCCR_USBCM_2                   0x00A00000
 #define SCCR_USBCM_3                   0x00F00000
 
-#define SCCR_CLK_MASK                  ( SCCR_TSEC1CM_3        \
-                                       | SCCR_TSEC2CM_3        \
-                                       | SCCR_ENCCM_3          \
-                                       | SCCR_USBCM_3          )
-
-#define SCCR_DEFAULT                   0xFFFFFFFF
-
 /* CSn_BDNS - Chip Select memory Bounds Register
  */
 #define CSBNDS_SA                      0x00FF0000