[new uImage] Do not compile new uImage format support by default

[u-boot] / include / mpc83xx.h

diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 39cecf21c2b52729d2b5a665fbf5e8a6ebfa9b37..df052e3d4c73fe2dcb62f13b5e5c7762e33a9e9d 100644 (file)
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -725,6 +725,7 @@
 #define SCCR_USBCM_3                   0x00F00000
 
 #elif defined(CONFIG_MPC8313)
+/* TSEC1 bits are for TSEC2 as well */
 #define SCCR_TSEC1CM                   0xc0000000
 #define SCCR_TSEC1CM_SHIFT             30
 #define SCCR_TSEC1CM_0                 0x00000000
@@ -732,13 +733,6 @@
 #define SCCR_TSEC1CM_2                 0x80000000
 #define SCCR_TSEC1CM_3                 0xC0000000
 
-#define SCCR_TSEC2CM                   0x30000000
-#define SCCR_TSEC2CM_SHIFT             28
-#define SCCR_TSEC2CM_0                 0x00000000
-#define SCCR_TSEC2CM_1                 0x10000000
-#define SCCR_TSEC2CM_2                 0x20000000
-#define SCCR_TSEC2CM_3                 0x30000000
-
 #define SCCR_TSEC1ON                   0x20000000
 #define SCCR_TSEC1ON_SHIFT             29
 #define SCCR_TSEC2ON                   0x10000000
@@ -838,6 +832,8 @@
 #define SCCR_PCIEXP2CM_3               0x000c0000
 
 /* All of the four SATA controllers must have the same clock ratio */
+#define SCCR_SATA1CM                   0x000000c0
+#define SCCR_SATA1CM_SHIFT             6
 #define SCCR_SATACM                    0x000000ff
 #define SCCR_SATACM_SHIFT              0
 #define SCCR_SATACM_0                  0x00000000