ddr: altera: Add ECC DRAM scrubbing support for Arria10

[u-boot] / include / mpc8xx.h

diff --git a/include/mpc8xx.h b/include/mpc8xx.h
index fc081ab7568e76ae0c09508b11d0434eb9c704d8..0e0e0cb70d7c3535e39817d921c01e9e82b5a346 100644 (file)
--- a/include/mpc8xx.h
+++ b/include/mpc8xx.h
@@ -1,8 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /*
@@ -81,7 +80,7 @@
 #define TBSCR_TBIRQ2   0x0400          /* Time Base Interrupt Request 2        */
 #define TBSCR_TBIRQ1   0x0200          /* Time Base Interrupt Request 1        */
 #define TBSCR_TBIRQ0   0x0100          /* Time Base Interrupt Request 0        */
-#if 0  /* already in asm/8xx_immap.h */
+#if 0  /* already in asm/immap_8xx.h */
 #define TBSCR_REFA     0x0080          /* Reference Interrupt Status A         */
 #define TBSCR_REFB     0x0040          /* Reference Interrupt Status B         */
 #define TBSCR_REFAE    0x0008          /* Second Interrupt Enable A            */
@@ -95,7 +94,7 @@
  */
 #undef PISCR_PIRQ                      /* TBD                                  */
 #define PISCR_PITF     0x0002          /* Periodic Interrupt Timer Freeze      */
-#if 0  /* already in asm/8xx_immap.h */
+#if 0  /* already in asm/immap_8xx.h */
 #define PISCR_PS       0x0080          /* Periodic interrupt Status            */
 #define PISCR_PIE      0x0004          /* Periodic Interrupt Enable            */
 #define PISCR_PTE      0x0001          /* Periodic Timer Enable                */