[PATCH] Update some AMCC 4xx board config files (set initrd_high)

[u-boot] / include / ppc405.h

diff --git a/include/ppc405.h b/include/ppc405.h
index 29e6ffd0d5f00ee8f7ccc9722e758365aeafe6af..e475fa54cdf27751bb90bf745661c9aa1aea7ad6 100644 (file)
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -132,9 +132,10 @@
 #define UIC_MAL_RXEOB 0x00080000      /* MAL RXEOB                          */
 #define UIC_MAL_TXDE  0x00040000      /* MAL TXDE                           */
 #define UIC_MAL_RXDE  0x00020000      /* MAL RXDE                           */
-#define UIC_ENET      0x00010000      /* Ethernet                           */
+#define UIC_ENET      0x00010000      /* Ethernet0                          */
+#define UIC_ENET1     0x00004000      /* Ethernet1 on 405EP                 */
+#define UIC_ECC_CE    0x00004000      /* ECC Correctable Error on 405GP     */
 #define UIC_EXT_PCI_SERR 0x00008000   /* External PCI SERR#                 */
-#define UIC_ECC_CE    0x00004000      /* ECC Correctable Error              */
 #define UIC_PCI_PM    0x00002000      /* PCI Power Management               */
 #define UIC_EXT0      0x00000040      /* External  interrupt 0              */
 #define UIC_EXT1      0x00000020      /* External  interrupt 1              */
@@ -159,6 +160,7 @@
   #define mem_bear    0x10    /* bus error address reg              */
 #endif
   #define mem_mcopt1  0x20    /* memory controller options 1        */
+  #define mem_status  0x24    /* memory status                      */
   #define mem_rtr     0x30    /* refresh timer reg                  */
   #define mem_pmit    0x34    /* power management idle timer        */
   #define mem_mb0cf   0x40    /* memory bank 0 configuration        */
@@ -480,6 +482,12 @@
 #define PLLMR1_266_133_66_33 (PLL_FBKDIV_8  |  \
                              PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
                              PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 |  \
+                             PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
+                             PLL_MALDIV_1 | PLL_PCIDIV_2)
+#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8  |  \
+                             PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+                             PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 
 /*
  * PLL Voltage Controlled Oscillator (VCO) definitions
@@ -556,12 +564,14 @@
 #define PSR_PCI_ARBIT_EN        0x00000400
 #define PSR_NEW_MODE_EN         0x00000020     /* PPC405GPr only */
 
+#ifndef CONFIG_IOP480
 /*
  * PLL Voltage Controlled Oscillator (VCO) definitions
  * Maximum and minimum values (in MHz) for correct PLL operation.
  */
 #define VCO_MIN     400
 #define VCO_MAX     800
+#endif /* #ifndef CONFIG_IOP480 */
 #endif /* #ifdef CONFIG_405EP */
 
 /******************************************************************************
@@ -582,8 +592,11 @@
 #define malrxdeir  (MAL_DCR_BASE+0x13)  /* RX Descr. Error Int reg           */
 #define maltxctp0r (MAL_DCR_BASE+0x20)  /* TX 0 Channel table pointer reg    */
 #define maltxctp1r (MAL_DCR_BASE+0x21)  /* TX 1 Channel table pointer reg    */
+#define maltxctp2r (MAL_DCR_BASE+0x22)  /* TX 2 Channel table pointer reg    */
 #define malrxctp0r (MAL_DCR_BASE+0x40)  /* RX 0 Channel table pointer reg    */
+#define malrxctp1r (MAL_DCR_BASE+0x41)  /* RX 1 Channel table pointer reg    */
 #define malrcbs0   (MAL_DCR_BASE+0x60)  /* RX 0 Channel buffer size reg      */
+#define malrcbs1   (MAL_DCR_BASE+0x61)  /* RX 1 Channel buffer size reg      */
 
 /*-----------------------------------------------------------------------------
 | IIC Register Offsets
@@ -671,6 +684,7 @@ typedef struct
   unsigned long freqPCI;
   unsigned long pciIntArbEn;            /* Internal PCI arbiter is enabled */
   unsigned long pciClkSync;             /* PCI clock is synchronous        */
+  unsigned long freqVCOHz;
 } PPC405_SYS_INFO;
 
 #endif  /* _ASMLANGUAGE */