Merge branch 'master' of git://www.denx.de/git/u-boot-video

[u-boot] / include / ppc440.h

diff --git a/include/ppc440.h b/include/ppc440.h
index 10517cbb6509e3fd9dd6e3500e79566ea5dde4ba..bb39ad63175dda78ca23c606e7612b57cb7f8938 100644 (file)
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1731,17 +1731,10 @@
 #else
 #define CNTRL_DCR_BASE 0x0b0
 #endif
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+
 #define cpc0_er                (CNTRL_DCR_BASE+0x00)   /* CPM enable register          */
 #define cpc0_fr                (CNTRL_DCR_BASE+0x01)   /* CPM force register           */
 #define cpc0_sr                (CNTRL_DCR_BASE+0x02)   /* CPM status register          */
-#else
-#define cpc0_sr                (CNTRL_DCR_BASE+0x00)   /* CPM status register          */
-#define cpc0_er                (CNTRL_DCR_BASE+0x01)   /* CPM enable register          */
-#define cpc0_fr                (CNTRL_DCR_BASE+0x02)   /* CPM force register           */
-#endif
 
 #define cpc0_sys0      (CNTRL_DCR_BASE+0x30)   /* System configuration reg 0   */
 #define cpc0_sys1      (CNTRL_DCR_BASE+0x31)   /* System configuration reg 1   */
@@ -2023,9 +2016,13 @@
 #define malrxctp2r  (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg   */
 #define malrxctp3r  (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg   */
 #define malrxctp8r  (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg   */
+#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table pointer reg  */
+#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table pointer reg  */
 #define malrcbs2    (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg            */
 #define malrcbs3    (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg            */
 #define malrcbs8    (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg            */
+#define malrcbs16   (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg    */
+#define malrcbs24   (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg    */
 #endif /* CONFIG_440GX */