Merge branch 'mpc86xx'

[u-boot] / include / ppc4xx_enet.h

diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h
index eacfb68016ea736759d9f572c3827f32d449fbd4..43c5ca451e09fb81cbd2ad64430f755845bc5a9a 100644 (file)
--- a/include/ppc4xx_enet.h
+++ b/include/ppc4xx_enet.h
@@ -131,15 +131,28 @@ typedef struct emac_4xx_hw_st {
 
 #if defined(CONFIG_440GX)
 #define EMAC_NUM_DEV       4
-#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && defined(CONFIG_NET_MULTI)
+#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) &&        \
+       defined(CONFIG_NET_MULTI) &&                    \
+       !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
 #define EMAC_NUM_DEV       2
 #else
 #define EMAC_NUM_DEV       1
 #endif
 
+#ifdef CONFIG_IBM_EMAC4_V4     /* EMAC4 V4 changed bit setting */
+#define EMAC_STACR_OC_MASK     (0x00008000)
+#else
+#define EMAC_STACR_OC_MASK     (0x00000000)
+#endif
+
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR0_PFC1_EM_1000      (0x00200000)
+#endif
 
 /*ZMII Bridge Register addresses */
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define ZMII_BASE                      (CFG_PERIPHERAL_BASE + 0x0D00)
 #else
 #define ZMII_BASE                      (CFG_PERIPHERAL_BASE + 0x0780)
@@ -152,6 +165,7 @@ typedef struct emac_4xx_hw_st {
 #define ZMII_MDI0                      0x80000000
 
 /* ZMII FER Register Bit Definitions */
+#define ZMII_FER_DIS           (0x0)
 #define ZMII_FER_MDI           (0x8)
 #define ZMII_FER_SMII          (0x4)
 #define ZMII_FER_RMII          (0x2)
@@ -186,7 +200,11 @@ typedef struct emac_4xx_hw_st {
 #define ZMII_SMIISR_V(__x)     ((3 - __x) * 8)
 
 /* RGMII Register Addresses */
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define RGMII_BASE             (CFG_PERIPHERAL_BASE + 0x1000)
+#else
 #define RGMII_BASE             (CFG_PERIPHERAL_BASE + 0x0790)
+#endif
 #define RGMII_FER              (RGMII_BASE + 0x00)
 #define RGMII_SSR              (RGMII_BASE + 0x04)
 
@@ -205,7 +223,11 @@ typedef struct emac_4xx_hw_st {
 #define RGMII_SSR_SP_100MBPS   (0x02)
 #define RGMII_SSR_SP_1000MBPS  (0x04)
 
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define RGMII_SSR_V(__x)       ((__x) * 8)
+#else
 #define RGMII_SSR_V(__x)       ((__x -2) * 8)
+#endif
 
 
 /*---------------------------------------------------------------------------+
@@ -275,7 +297,8 @@ typedef struct emac_4xx_hw_st {
 
 /* Ethernet MAC Regsiter Addresses */
 #if defined(CONFIG_440)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define EMAC_BASE                          (CFG_PERIPHERAL_BASE + 0x0E00)
 #else
 #define EMAC_BASE                          (CFG_PERIPHERAL_BASE + 0x0800)
@@ -321,7 +344,9 @@ typedef struct emac_4xx_hw_st {
 #define EMAC_M0_WKE                        (0x04000000)
 
 /* on 440GX EMAC_MR1 has a different layout! */
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 /* MODE Reg 1 */
 #define EMAC_M1_FDE            (0x80000000)
 #define EMAC_M1_ILE            (0x40000000)
@@ -422,8 +447,21 @@ typedef struct emac_4xx_hw_st {
 /* STA CONTROL REG */
 #define EMAC_STACR_OC                  (0x00008000)
 #define EMAC_STACR_PHYE                        (0x00004000)
+
+#ifdef CONFIG_IBM_EMAC4_V4     /* EMAC4 V4 changed bit setting */
+#define EMAC_STACR_INDIRECT_MODE       (0x00002000)
+#define EMAC_STACR_WRITE               (0x00000800) /* $BUC */
+#define EMAC_STACR_READ                        (0x00001000) /* $BUC */
+#define EMAC_STACR_OP_MASK             (0x00001800)
+#define EMAC_STACR_MDIO_ADDR           (0x00000000)
+#define EMAC_STACR_MDIO_WRITE          (0x00000800)
+#define EMAC_STACR_MDIO_READ           (0x00001800)
+#define EMAC_STACR_MDIO_READ_INC       (0x00001000)
+#else
 #define EMAC_STACR_WRITE               (0x00002000)
 #define EMAC_STACR_READ                        (0x00001000)
+#endif
+
 #define EMAC_STACR_CLK_83MHZ   (0x00000800)  /* 0's for 50Mhz */
 #define EMAC_STACR_CLK_66MHZ   (0x00000400)
 #define EMAC_STACR_CLK_100MHZ  (0x00000C00)