sdhci: Add new sdhci ops for platform specific tuning and delays

[u-boot] / include / sdhci.h

diff --git a/include/sdhci.h b/include/sdhci.h
index 7544b494b1632f80a6da118a38b5846c744743e2..8ca632f3e0beba23c4b5b77ff878189729e46269 100644 (file)
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -1,9 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2011, Marvell Semiconductor Inc.
  * Lei Wen <leiwen@marvell.com>
  *
- * SPDX-License-Identifier:    GPL-2.0+
- *
  * Back ported to the 8xx platform (from the 8260 platform) by
  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  */
@@ -213,6 +212,12 @@
 #define SDHCI_QUIRK_BROKEN_R1B         (1 << 2)
 #define SDHCI_QUIRK_NO_HISPD_BIT       (1 << 3)
 #define SDHCI_QUIRK_BROKEN_VOLTAGE     (1 << 4)
+/*
+ * SDHCI_QUIRK_BROKEN_HISPD_MODE
+ * the hardware cannot operate correctly in high-speed mode,
+ * this quirk forces the sdhci host-controller to non high-speed mode
+ */
+#define SDHCI_QUIRK_BROKEN_HISPD_MODE  BIT(5)
 #define SDHCI_QUIRK_WAIT_SEND_CMD      (1 << 6)
 #define SDHCI_QUIRK_USE_WIDE8          (1 << 8)
 
@@ -235,7 +240,10 @@ struct sdhci_ops {
 #endif
        int     (*get_cd)(struct sdhci_host *host);
        void    (*set_control_reg)(struct sdhci_host *host);
+       void    (*set_ios_post)(struct sdhci_host *host);
        void    (*set_clock)(struct sdhci_host *host, u32 div);
+       int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
+       void (*set_delay)(struct sdhci_host *host);
 };
 
 struct sdhci_host {
@@ -244,6 +252,7 @@ struct sdhci_host {
        unsigned int quirks;
        unsigned int host_caps;
        unsigned int version;
+       unsigned int max_clk;   /* Maximum Base Clock frequency */
        unsigned int clk_mul;   /* Clock Multiplier value */
        unsigned int clock;
        struct mmc *mmc;
@@ -371,11 +380,11 @@ static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
  *
  * @cfg:       Configuration structure to fill in (generally &plat->mmc)
  * @host:      SDHCI host structure
- * @max_clk:   Maximum supported clock speed in HZ (0 for default)
- * @min_clk:   Minimum supported clock speed in HZ (0 for default)
+ * @f_max:     Maximum supported clock frequency in HZ (0 for default)
+ * @f_min:     Minimum supported clock frequency in HZ (0 for default)
  */
 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
-                   u32 max_clk, u32 min_clk);
+                   u32 f_max, u32 f_min);
 
 /**
  * sdhci_bind() - Set up a new MMC block device
@@ -401,14 +410,14 @@ int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
  * This is used when you are not using CONFIG_BLK. Convert your driver over!
  *
  * @host:      SDHCI host structure
- * @max_clk:   Maximum supported clock speed in HZ (0 for default)
- * @min_clk:   Minimum supported clock speed in HZ (0 for default)
+ * @f_max:     Maximum supported clock frequency in HZ (0 for default)
+ * @f_min:     Minimum supported clock frequency in HZ (0 for default)
  * @return 0 if OK, -ve on error
  */
-int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk);
+int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
 #endif /* !CONFIG_BLK */
 
-#ifdef CONFIG_DM_MMC_OPS
+#ifdef CONFIG_DM_MMC
 /* Export the operations to drivers */
 int sdhci_probe(struct udevice *dev);
 extern const struct dm_mmc_ops sdhci_ops;