include: reset: Change to use CONFIG_IS_ENABLED(DM_RESET)

[u-boot] / include / sdhci.h

diff --git a/include/sdhci.h b/include/sdhci.h
index 7e84012f60ec2b840a6abd64c139282e48baa37b..bef37df982e4e9e17d3a223d4c81377812f4bb13 100644 (file)
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -1,9 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2011, Marvell Semiconductor Inc.
  * Lei Wen <leiwen@marvell.com>
  *
- * SPDX-License-Identifier:    GPL-2.0+
- *
  * Back ported to the 8xx platform (from the 8260 platform) by
  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  */
@@ -167,6 +166,11 @@
 #define  SDHCI_CAN_64BIT       BIT(28)
 
 #define SDHCI_CAPABILITIES_1   0x44
+#define  SDHCI_SUPPORT_SDR50   0x00000001
+#define  SDHCI_SUPPORT_SDR104  0x00000002
+#define  SDHCI_SUPPORT_DDR50   0x00000004
+#define  SDHCI_USE_SDR50_TUNING        0x00002000
+
 #define  SDHCI_CLOCK_MUL_MASK  0x00FF0000
 #define  SDHCI_CLOCK_MUL_SHIFT 16
 
@@ -213,8 +217,15 @@
 #define SDHCI_QUIRK_BROKEN_R1B         (1 << 2)
 #define SDHCI_QUIRK_NO_HISPD_BIT       (1 << 3)
 #define SDHCI_QUIRK_BROKEN_VOLTAGE     (1 << 4)
+/*
+ * SDHCI_QUIRK_BROKEN_HISPD_MODE
+ * the hardware cannot operate correctly in high-speed mode,
+ * this quirk forces the sdhci host-controller to non high-speed mode
+ */
+#define SDHCI_QUIRK_BROKEN_HISPD_MODE  BIT(5)
 #define SDHCI_QUIRK_WAIT_SEND_CMD      (1 << 6)
 #define SDHCI_QUIRK_USE_WIDE8          (1 << 8)
+#define SDHCI_QUIRK_NO_1_8_V           (1 << 9)
 
 /* to make gcc happy */
 struct sdhci_host;
@@ -237,6 +248,8 @@ struct sdhci_ops {
        void    (*set_control_reg)(struct sdhci_host *host);
        void    (*set_ios_post)(struct sdhci_host *host);
        void    (*set_clock)(struct sdhci_host *host, u32 div);
+       int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
+       void (*set_delay)(struct sdhci_host *host);
 };
 
 struct sdhci_host {