+/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) Copyright 2015 Xilinx, Inc,
* Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ZYNQMPPL_H_
#define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID 0xC2000018
#define ZYNQMP_SIP_SVC_PM_FPGA_LOAD 0xC2000016
+#define ZYNQMP_SIP_SVC_PM_FPGA_STATUS 0xC2000017
#define ZYNQMP_FPGA_OP_INIT (1 << 0)
#define ZYNQMP_FPGA_OP_LOAD (1 << 1)
#define ZYNQMP_FPGA_OP_DONE (1 << 2)