+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2011 The Chromium OS Authors.
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef USE_HOSTCC
#include <errno.h>
#include <fdtdec.h>
#include <fdt_support.h>
-#include <libfdt.h>
+#include <inttypes.h>
+#include <linux/libfdt.h>
#include <serial.h>
#include <asm/sections.h>
#include <linux/ctype.h>
COMPAT(SAMSUNG_EXYNOS_MIPI_DSI, "samsung,exynos-mipi-dsi"),
COMPAT(SAMSUNG_EXYNOS_DWMMC, "samsung,exynos-dwmmc"),
COMPAT(SAMSUNG_EXYNOS_MMC, "samsung,exynos-mmc"),
- COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686"),
COMPAT(GENERIC_SPI_FLASH, "spi-flash"),
COMPAT(MAXIM_98095_CODEC, "maxim,max98095-codec"),
COMPAT(SAMSUNG_EXYNOS5_I2C, "samsung,exynos5-hsi2c"),
COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
COMPAT(ALTERA_SOCFPGA_FPGA0, "altr,socfpga-a10-fpga-mgr"),
COMPAT(ALTERA_SOCFPGA_NOC, "altr,socfpga-a10-noc"),
+ COMPAT(ALTERA_SOCFPGA_CLK_INIT, "altr,socfpga-a10-clk-init")
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
addr->phys_mid = fdt32_to_cpu(cell[1]);
addr->phys_lo = fdt32_to_cpu(cell[1]);
break;
- } else {
- cell += (FDT_PCI_ADDR_CELLS +
- FDT_PCI_SIZE_CELLS);
}
+
+ cell += (FDT_PCI_ADDR_CELLS +
+ FDT_PCI_SIZE_CELLS);
}
if (i == num) {
}
return 0;
- } else {
- ret = -EINVAL;
}
+ ret = -EINVAL;
+
fail:
debug("(not found)\n");
return ret;
end = list + len;
while (list < end) {
- char *s;
-
len = strlen(list);
if (len >= strlen("pciVVVV,DDDD")) {
- s = strstr(list, "pci");
+ char *s = strstr(list, "pci");
/*
* check if the string is something like pciVVVV,DDDD.RR
/* extract the bar number from fdt_pci_addr */
barnum = addr->phys_hi & 0xff;
- if ((barnum < PCI_BASE_ADDRESS_0) || (barnum > PCI_CARDBUS_CIS))
+ if (barnum < PCI_BASE_ADDRESS_0 || barnum > PCI_CARDBUS_CIS)
return -EINVAL;
barnum = (barnum - PCI_BASE_ADDRESS_0) / 4;
*/
cell = fdt_getprop(blob, node, "status", NULL);
if (cell)
- return 0 == strcmp(cell, "okay");
+ return strcmp(cell, "okay") == 0;
return 1;
}
/* Search our drivers */
for (id = COMPAT_UNKNOWN; id < COMPAT_COUNT; id++)
- if (0 == fdt_node_check_compatible(blob, node,
- compat_names[id]))
+ if (fdt_node_check_compatible(blob, node,
+ compat_names[id]) == 0)
return id;
return COMPAT_UNKNOWN;
}
u32 *array, int count)
{
const u32 *cell;
- int i, err = 0;
+ int err = 0;
debug("%s: %s\n", __func__, prop_name);
cell = get_prop_check_min_len(blob, node, prop_name,
sizeof(u32) * count, &err);
if (!err) {
+ int i;
+
for (i = 0; i < count; i++)
array[i] = fdt32_to_cpu(cell[i]);
}
while (ptr + na + ns <= end) {
if (i == index) {
- res->start = res->end = fdtdec_get_number(ptr, na);
+ res->start = fdtdec_get_number(ptr, na);
+ res->end = res->start;
res->end += fdtdec_get_number(&ptr[na], ns) - 1;
return 0;
}
# endif
# ifndef CONFIG_SPL_BUILD
/* Allow the early environment to override the fdt address */
+# if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
+ gd->fdt_blob = (void *)prior_stage_fdt_address;
+# else
gd->fdt_blob = (void *)env_get_ulong("fdtcontroladdr", 16,
(uintptr_t)gd->fdt_blob);
+# endif
# endif
# if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
return fdtdec_prepare_fdt();
}
+#ifdef CONFIG_NR_DRAM_BANKS
+int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id,
+ phys_addr_t *basep, phys_size_t *sizep, bd_t *bd)
+{
+ int addr_cells, size_cells;
+ const u32 *cell, *end;
+ u64 total_size, size, addr;
+ int node, child;
+ bool auto_size;
+ int bank;
+ int len;
+
+ debug("%s: board_id=%d\n", __func__, board_id);
+ if (!area)
+ area = "/memory";
+ node = fdt_path_offset(blob, area);
+ if (node < 0) {
+ debug("No %s node found\n", area);
+ return -ENOENT;
+ }
+
+ cell = fdt_getprop(blob, node, "reg", &len);
+ if (!cell) {
+ debug("No reg property found\n");
+ return -ENOENT;
+ }
+
+ addr_cells = fdt_address_cells(blob, node);
+ size_cells = fdt_size_cells(blob, node);
+
+ /* Check the board id and mask */
+ for (child = fdt_first_subnode(blob, node);
+ child >= 0;
+ child = fdt_next_subnode(blob, child)) {
+ int match_mask, match_value;
+
+ match_mask = fdtdec_get_int(blob, child, "match-mask", -1);
+ match_value = fdtdec_get_int(blob, child, "match-value", -1);
+
+ if (match_value >= 0 &&
+ ((board_id & match_mask) == match_value)) {
+ /* Found matching mask */
+ debug("Found matching mask %d\n", match_mask);
+ node = child;
+ cell = fdt_getprop(blob, node, "reg", &len);
+ if (!cell) {
+ debug("No memory-banks property found\n");
+ return -EINVAL;
+ }
+ break;
+ }
+ }
+ /* Note: if no matching subnode was found we use the parent node */
+
+ if (bd) {
+ memset(bd->bi_dram, '\0', sizeof(bd->bi_dram[0]) *
+ CONFIG_NR_DRAM_BANKS);
+ }
+
+ auto_size = fdtdec_get_bool(blob, node, "auto-size");
+
+ total_size = 0;
+ end = cell + len / 4 - addr_cells - size_cells;
+ debug("cell at %p, end %p\n", cell, end);
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ if (cell > end)
+ break;
+ addr = 0;
+ if (addr_cells == 2)
+ addr += (u64)fdt32_to_cpu(*cell++) << 32UL;
+ addr += fdt32_to_cpu(*cell++);
+ if (bd)
+ bd->bi_dram[bank].start = addr;
+ if (basep && !bank)
+ *basep = (phys_addr_t)addr;
+
+ size = 0;
+ if (size_cells == 2)
+ size += (u64)fdt32_to_cpu(*cell++) << 32UL;
+ size += fdt32_to_cpu(*cell++);
+
+ if (auto_size) {
+ u64 new_size;
+
+ debug("Auto-sizing %" PRIx64 ", size %" PRIx64 ": ",
+ addr, size);
+ new_size = get_ram_size((long *)(uintptr_t)addr, size);
+ if (new_size == size) {
+ debug("OK\n");
+ } else {
+ debug("sized to %" PRIx64 "\n", new_size);
+ size = new_size;
+ }
+ }
+
+ if (bd)
+ bd->bi_dram[bank].size = size;
+ total_size += size;
+ }
+
+ debug("Memory size %" PRIu64 "\n", total_size);
+ if (sizep)
+ *sizep = (phys_size_t)total_size;
+
+ return 0;
+}
+#endif /* CONFIG_NR_DRAM_BANKS */
+
#endif /* !USE_HOSTCC */
projects / u-boot / blobdiff