FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.

[u-boot] / lib_ppc / bat_rw.c

diff --git a/lib_ppc/bat_rw.c b/lib_ppc/bat_rw.c
index 8546333868de00792ae91296ed235a593b0372bc..a40b377bcaac14947a7a04748c305551bd4a73b2 100644 (file)
--- a/lib_ppc/bat_rw.c
+++ b/lib_ppc/bat_rw.c
@@ -25,9 +25,12 @@
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
+#include <asm/io.h>
 
 int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
 {
+       sync();
+
        switch (bat) {
        case DBAT0:
                mtspr (DBAT0L, lower);
@@ -99,6 +102,9 @@ int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
                return (-1);
        }
 
+       sync();
+       isync();
+
        return (0);
 }