Consolidate arch-specific sbrk() implementations

[u-boot] / lib_ppc / bat_rw.c

diff --git a/lib_ppc/bat_rw.c b/lib_ppc/bat_rw.c
index 5f01a63f2af25a7540846aea813a0b02e9c0a2b6..c48c24015153ade7180d6accc9e62968127e792d 100644 (file)
--- a/lib_ppc/bat_rw.c
+++ b/lib_ppc/bat_rw.c
@@ -25,13 +25,25 @@
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_ADDR_MAP
+#include <addr_map.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
 
 int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
 {
+       int batn = -1;
+
+       sync();
+
        switch (bat) {
        case DBAT0:
                mtspr (DBAT0L, lower);
                mtspr (DBAT0U, upper);
+               batn = 0;
                break;
        case IBAT0:
                mtspr (IBAT0L, lower);
@@ -40,6 +52,7 @@ int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
        case DBAT1:
                mtspr (DBAT1L, lower);
                mtspr (DBAT1U, upper);
+               batn = 1;
                break;
        case IBAT1:
                mtspr (IBAT1L, lower);
@@ -48,6 +61,7 @@ int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
        case DBAT2:
                mtspr (DBAT2L, lower);
                mtspr (DBAT2U, upper);
+               batn = 2;
                break;
        case IBAT2:
                mtspr (IBAT2L, lower);
@@ -56,6 +70,7 @@ int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
        case DBAT3:
                mtspr (DBAT3L, lower);
                mtspr (DBAT3U, upper);
+               batn = 3;
                break;
        case IBAT3:
                mtspr (IBAT3L, lower);
@@ -65,6 +80,7 @@ int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
        case DBAT4:
                mtspr (DBAT4L, lower);
                mtspr (DBAT4U, upper);
+               batn = 4;
                break;
        case IBAT4:
                mtspr (IBAT4L, lower);
@@ -73,6 +89,7 @@ int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
        case DBAT5:
                mtspr (DBAT5L, lower);
                mtspr (DBAT5U, upper);
+               batn = 5;
                break;
        case IBAT5:
                mtspr (IBAT5L, lower);
@@ -81,6 +98,7 @@ int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
        case DBAT6:
                mtspr (DBAT6L, lower);
                mtspr (DBAT6U, upper);
+               batn = 6;
                break;
        case IBAT6:
                mtspr (IBAT6L, lower);
@@ -89,6 +107,7 @@ int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
        case DBAT7:
                mtspr (DBAT7L, lower);
                mtspr (DBAT7U, upper);
+               batn = 7;
                break;
        case IBAT7:
                mtspr (IBAT7L, lower);
@@ -99,6 +118,21 @@ int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
                return (-1);
        }
 
+#ifdef CONFIG_ADDR_MAP
+       if ((gd->flags & GD_FLG_RELOC) && (batn >= 0)) {
+               phys_size_t size;
+               if (!BATU_VALID(upper))
+                       size = 0;
+               else
+                       size = BATU_SIZE(upper);
+               addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower),
+                                 size, batn);
+       }
+#endif
+
+       sync();
+       isync();
+
        return (0);
 }
 
@@ -183,3 +217,44 @@ int read_bat (ppc_bat_t bat, unsigned long *upper, unsigned long *lower)
 
        return (0);
 }
+
+void print_bats(void)
+{
+       printf("BAT registers:\n");
+
+       printf ("\tIBAT0L = 0x%08X ", mfspr (IBAT0L));
+       printf ("\tIBAT0U = 0x%08X\n", mfspr (IBAT0U));
+       printf ("\tDBAT0L = 0x%08X ", mfspr (DBAT0L));
+       printf ("\tDBAT0U = 0x%08X\n", mfspr (DBAT0U));
+       printf ("\tIBAT1L = 0x%08X ", mfspr (IBAT1L));
+       printf ("\tIBAT1U = 0x%08X\n", mfspr (IBAT1U));
+       printf ("\tDBAT1L = 0x%08X ", mfspr (DBAT1L));
+       printf ("\tDBAT1U = 0x%08X\n", mfspr (DBAT1U));
+       printf ("\tIBAT2L = 0x%08X ", mfspr (IBAT2L));
+       printf ("\tIBAT2U = 0x%08X\n", mfspr (IBAT2U));
+       printf ("\tDBAT2L = 0x%08X ", mfspr (DBAT2L));
+       printf ("\tDBAT2U = 0x%08X\n", mfspr (DBAT2U));
+       printf ("\tIBAT3L = 0x%08X ", mfspr (IBAT3L));
+       printf ("\tIBAT3U = 0x%08X\n", mfspr (IBAT3U));
+       printf ("\tDBAT3L = 0x%08X ", mfspr (DBAT3L));
+       printf ("\tDBAT3U = 0x%08X\n", mfspr (DBAT3U));
+
+#ifdef CONFIG_HIGH_BATS
+       printf ("\tIBAT4L = 0x%08X ", mfspr (IBAT4L));
+       printf ("\tIBAT4U = 0x%08X\n", mfspr (IBAT4U));
+       printf ("\tDBAT4L = 0x%08X ", mfspr (DBAT4L));
+       printf ("\tDBAT4U = 0x%08X\n", mfspr (DBAT4U));
+       printf ("\tIBAT5L = 0x%08X ", mfspr (IBAT5L));
+       printf ("\tIBAT5U = 0x%08X\n", mfspr (IBAT5U));
+       printf ("\tDBAT5L = 0x%08X ", mfspr (DBAT5L));
+       printf ("\tDBAT5U = 0x%08X\n", mfspr (DBAT5U));
+       printf ("\tIBAT6L = 0x%08X ", mfspr (IBAT6L));
+       printf ("\tIBAT6U = 0x%08X\n", mfspr (IBAT6U));
+       printf ("\tDBAT6L = 0x%08X ", mfspr (DBAT6L));
+       printf ("\tDBAT6U = 0x%08X\n", mfspr (DBAT6U));
+       printf ("\tIBAT7L = 0x%08X ", mfspr (IBAT7L));
+       printf ("\tIBAT7U = 0x%08X\n", mfspr (IBAT7U));
+       printf ("\tDBAT7L = 0x%08X ", mfspr (DBAT7L));
+       printf ("\tDBAT7U = 0x%08X\n", mfspr (DBAT7U));
+#endif
+}