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[cc65] / libsrc / lynx / crt0.s

diff --git a/libsrc/lynx/crt0.s b/libsrc/lynx/crt0.s
index a7252f84792400b771de3c972f685994fe5296cf..116b39f76a26b11b229642a91b1d13281ad19062 100644 (file)
--- a/libsrc/lynx/crt0.s
+++ b/libsrc/lynx/crt0.s
@@ -15,24 +15,23 @@
 ; on the front of the fully linked binary (see EXEHDR segment.)
 ;
 
-       .include        "lynx.inc"
-       .export         _exit
+        .export         _exit
         .export         __STARTUP__ : absolute = 1      ; Mark as startup
 
-       .import         callirq, initlib, donelib
-       .import         zerobss
-       .import         callmain
-       .import         _main
-       .import         __INTERRUPTOR_COUNT__
-       .import         __RAM_START__, __RAM_SIZE__, __STACKSIZE__
+        .import         initlib, donelib
+        .import         zerobss
+        .import         callmain
+        .import         _main
+        .import         __RAM_START__, __RAM_SIZE__, __STACKSIZE__
 
-       .include        "zeropage.inc"
+        .include        "zeropage.inc"
         .include        "extzp.inc"
+        .include        "lynx.inc"
 
 ; ------------------------------------------------------------------------
 ; Mikey and Suzy init data, reg offsets and data
 
-       .rodata
+        .rodata
 
 SuzyInitReg:    .byte $28,$2a,$04,$06,$92,$83,$90
 SuzyInitData:   .byte $7f,$7f,$00,$00,$24,$f3,$01
@@ -40,101 +39,89 @@ SuzyInitData:   .byte $7f,$7f,$00,$00,$24,$f3,$01
 MikeyInitReg:   .byte $00,$01,$08,$09,$20,$28,$30,$38,$44,$50,$8a,$8b,$8c,$92,$93
 MikeyInitData:  .byte $9e,$18,$68,$1f,$00,$00,$00,$00,$00,$ff,$1a,$1b,$04,$0d,$29
 
-
 ; ------------------------------------------------------------------------
 ; Actual code
 
-       .segment "STARTUP"
+        .segment "STARTUP"
 
 ; set up system
 
-       sei
-       cld
-       ldx     #$FF
-       txs
+        sei
+        cld
+        ldx     #$FF
+        txs
 
 ; init bank switching
 
-               lda     #$C
-               sta     MAPCTL                  ; $FFF9
+        lda     #$C
+        sta     MAPCTL          ; $FFF9
 
 ; disable all timer interrupts
 
-               lda     #$80
-               trb     TIM0CTLA
-               trb     TIM1CTLA
-               trb     TIM2CTLA
-               trb     TIM3CTLA
-               trb     TIM5CTLA
-               trb     TIM6CTLA
-               trb     TIM7CTLA
+        lda     #$80
+        trb     TIM0CTLA
+        trb     TIM1CTLA
+        trb     TIM2CTLA
+        trb     TIM3CTLA
+        trb     TIM5CTLA
+        trb     TIM6CTLA
+        trb     TIM7CTLA
 
 ; disable TX/RX IRQ, set to 8E1
 
-               lda     #%11101
-               sta     SERCTL
+        lda     #%11101
+        sta     SERCTL
 
 ; clear all pending interrupts
 
-               lda     INTSET
-               sta     INTRST
+        lda     INTSET
+        sta     INTRST
 
 ; setup the stack
 
-       lda     #<(__RAM_START__ + __RAM_SIZE__ + __STACKSIZE__)
-       sta     sp
-       lda     #>(__RAM_START__ + __RAM_SIZE__ + __STACKSIZE__)
-       sta     sp+1
+        lda     #<(__RAM_START__ + __RAM_SIZE__ + __STACKSIZE__)
+        sta     sp
+        lda     #>(__RAM_START__ + __RAM_SIZE__ + __STACKSIZE__)
+        sta     sp+1
 
 ; Init Mickey
 
-       ldx     #.sizeof(MikeyInitReg)-1
+        ldx     #.sizeof(MikeyInitReg)-1
 mloop:  ldy     MikeyInitReg,x
-       lda     MikeyInitData,x
-       sta     $fd00,y
-       dex
-       bpl     mloop
+        lda     MikeyInitData,x
+        sta     $fd00,y
+        dex
+        bpl     mloop
 
 ; these are RAM-shadows of read only regs
 
-       ldx     #$1b
-       stx     __iodat
-       dex                             ; $1A
-               stx     __iodir
-       ldx     #$d
-       stx     __viddma
+        ldx     #$1b
+        stx     __iodat
+        dex                     ; $1A
+        stx     __iodir
+        ldx     #$d
+        stx     __viddma
 
 ; Init Suzy
 
-       ldx     #.sizeof(SuzyInitReg)-1
+        ldx     #.sizeof(SuzyInitReg)-1
 sloop:  ldy     SuzyInitReg,x
-       lda     SuzyInitData,x
-       sta     $fc00,y
-       dex
-       bpl     sloop
+        lda     SuzyInitData,x
+        sta     $fc00,y
+        dex
+        bpl     sloop
 
-       lda     #$24
-       sta     __sprsys
+        lda     #$24
+        sta     __sprsys
+        cli
 
 ; Clear the BSS data
 
-       jsr     zerobss
-
-; If we have IRQ functions, set the IRQ vector
-; as Lynx is a console there is not much point in releasing the IRQ
-
-        lda     #<__INTERRUPTOR_COUNT__
-       beq     NoIRQ1
-       lda     #<IRQStub
-       ldx     #>IRQStub
-       sei
-       sta     INTVECTL
-       stx     INTVECTH
-       cli
+        jsr     zerobss
 
 ; Call module constructors
 
-NoIRQ1: jsr     initlib
+        jsr     initlib
 
 ; Push arguments and call main
 
@@ -147,19 +134,3 @@ _exit:  jsr     donelib         ; Run module destructors
 ; Endless loop
 
 noret:  bra     noret
-
-
-       .segment "CODE"
-IRQStub:
-       phy
-       phx
-       pha
-       cld
-               jsr     callirq
-       lda     INTSET
-       sta     INTRST
-       pla
-       plx
-       ply
-       rti
-