Merge branch 'next' of git://git.denx.de/u-boot-mpc83xx

[u-boot] / post / cpu / ppc4xx / spr.c

diff --git a/post/cpu/ppc4xx/spr.c b/post/cpu/ppc4xx/spr.c
index 3e746343d151770162e214df59b6f60e300ada16..9a3cdb3cf8026c84561035f3c402679f276dacab 100644 (file)
--- a/post/cpu/ppc4xx/spr.c
+++ b/post/cpu/ppc4xx/spr.c
@@ -4,23 +4,7 @@
  *
  * Author: Igor Lisitsin <igor@emcraft.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -35,14 +19,18 @@
  * corresponding table value.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
-#if CONFIG_POST & CFG_POST_SPR
+#if CONFIG_POST & CONFIG_SYS_POST_SPR
 
 #include <asm/processor.h>
 
+#ifdef CONFIG_4xx_DCACHE
+#include <asm/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 static struct {
        int number;
        char * name;
@@ -65,14 +53,16 @@ static struct {
 
        /* Additional Special-Purpose Registers.
         * The values must match the initialization
-        * values from cpu/ppc4xx/start.S
+        * values from arch/powerpc/cpu/ppc4xx/start.S
         */
        {0x30,  "PID",          0x00000000,     0x00000000},
        {0x3a,  "CSRR0",        0x00000000,     0x00000000},
        {0x3b,  "CSRR1",        0x00000000,     0x00000000},
        {0x3d,  "DEAR",         0x00000000,     0x00000000},
        {0x3e,  "ESR",          0x00000000,     0x00000000},
+#ifdef CONFIG_440
        {0x3f,  "IVPR",         0xffff0000,     0x00000000},
+#endif
        {0x100, "USPRG0",       0x00000000,     0x00000000},
        {0x104, "SPRG4",        0x00000000,     0x00000000},
        {0x105, "SPRG5",        0x00000000,     0x00000000},
@@ -80,7 +70,9 @@ static struct {
        {0x107, "SPRG7",        0x00000000,     0x00000000},
        {0x10c, "TBL",          0x00000000,     0x00000000},
        {0x10d, "TBU",          0x00000000,     0x00000000},
+#ifdef CONFIG_440
        {0x11e, "PIR",          0x0000000f,     0x00000000},
+#endif
        {0x130, "DBSR",         0x00000000,     0x00000000},
        {0x134, "DBCR0",        0x00000000,     0x00000000},
        {0x135, "DBCR1",        0x00000000,     0x00000000},
@@ -95,6 +87,7 @@ static struct {
        {0x13f, "DVC2",         0x00000000,     0x00000000},
        {0x150, "TSR",          0x00000000,     0x00000000},
        {0x154, "TCR",          0x00000000,     0x00000000},
+#ifdef CONFIG_440
        {0x190, "IVOR0",        0x0000fff0,     0x00000100},
        {0x191, "IVOR1",        0x0000fff0,     0x00000200},
        {0x192, "IVOR2",        0x0000fff0,     0x00000300},
@@ -111,6 +104,7 @@ static struct {
        {0x19d, "IVOR13",       0x0000fff0,     0x00001300},
        {0x19e, "IVOR14",       0x0000fff0,     0x00001400},
        {0x19f, "IVOR15",       0x0000fff0,     0x00002000},
+#endif
        {0x23a, "MCSRR0",       0x00000000,     0x00000000},
        {0x23b, "MCSRR1",       0x00000000,     0x00000000},
        {0x23c, "MCSR",         0x00000000,     0x00000000},
@@ -131,8 +125,10 @@ static struct {
        {0x395, "DTV1",         0x00000000,     0x00000000},
        {0x396, "DTV2",         0x00000000,     0x00000000},
        {0x397, "DTV3",         0x00000000,     0x00000000},
+#ifdef CONFIG_440
        {0x398, "DVLIM",        0x0fc1f83f,     0x0001f800},
        {0x399, "IVLIM",        0x0fc1f83f,     0x0001f800},
+#endif
        {0x39b, "RSTCFG",       0x00000000,     0x00000000},
        {0x39c, "DCDBTRL",      0x00000000,     0x00000000},
        {0x39d, "DCDBTRH",      0x00000000,     0x00000000},
@@ -144,8 +140,7 @@ static struct {
        {0x3f3, "DBDR",         0x00000000,     0x00000000},
 };
 
-static int spr_test_list_size =
-               sizeof (spr_test_list) / sizeof (spr_test_list[0]);
+static int spr_test_list_size = ARRAY_SIZE(spr_test_list);
 
 int spr_post_test (int flags)
 {
@@ -158,6 +153,10 @@ int spr_post_test (int flags)
        };
        unsigned long (*get_spr) (void) = (void *) code;
 
+#ifdef CONFIG_4xx_DCACHE
+       /* disable cache */
+       change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
+#endif
        for (i = 0; i < spr_test_list_size; i++) {
                int num = spr_test_list[i].number;
 
@@ -174,9 +173,12 @@ int spr_post_test (int flags)
                        ret = -1;
                }
        }
+#ifdef CONFIG_4xx_DCACHE
+       /* enable cache */
+       change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
+#endif
 
        return ret;
 }
 
-#endif /* CONFIG_POST & CFG_POST_SPR */
-#endif /* CONFIG_POST */
+#endif /* CONFIG_POST & CONFIG_SYS_POST_SPR */