#include <post.h>
#include <watchdog.h>
-#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
+#if CONFIG_POST & (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_MEM_REGIONS)
DECLARE_GLOBAL_DATA_PTR;
hi = (temp64>>32) & 0xffffffff;
lo = temp64 & 0xffffffff;
- post_log ("Memory (date line) error at %08x, "
+ post_log("Memory (date line) error at %08x, "
"wrote %08x%08x, read %08x%08x !\n",
pmem, pathi, patlo, hi, lo);
ret = -1;
}
#endif
if(readback == *testaddr) {
- post_log ("Memory (address line) error at %08x<->%08x, "
+ post_log("Memory (address line) error at %08x<->%08x, "
"XOR value %08x !\n",
testaddr, target, xor);
ret = -1;
return ret;
}
-static int memory_post_test1 (unsigned long start,
+static int memory_post_test1(unsigned long start,
unsigned long size,
unsigned long val)
{
for (i = 0; i < size / sizeof (ulong); i++) {
mem[i] = val;
if (i % 1024 == 0)
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
}
- for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
+ for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
readback = mem[i];
if (readback != val) {
- post_log ("Memory error at %08x, "
+ post_log("Memory error at %08x, "
"wrote %08x, read %08x !\n",
mem + i, val, readback);
break;
}
if (i % 1024 == 0)
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
}
return ret;
}
-static int memory_post_test2 (unsigned long start, unsigned long size)
+static int memory_post_test2(unsigned long start, unsigned long size)
{
unsigned long i;
ulong *mem = (ulong *) start;
for (i = 0; i < size / sizeof (ulong); i++) {
mem[i] = 1 << (i % 32);
if (i % 1024 == 0)
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
}
- for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
+ for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
readback = mem[i];
if (readback != (1 << (i % 32))) {
- post_log ("Memory error at %08x, "
+ post_log("Memory error at %08x, "
"wrote %08x, read %08x !\n",
mem + i, 1 << (i % 32), readback);
break;
}
if (i % 1024 == 0)
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
}
return ret;
}
-static int memory_post_test3 (unsigned long start, unsigned long size)
+static int memory_post_test3(unsigned long start, unsigned long size)
{
unsigned long i;
ulong *mem = (ulong *) start;
for (i = 0; i < size / sizeof (ulong); i++) {
mem[i] = i;
if (i % 1024 == 0)
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
}
- for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
+ for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
readback = mem[i];
if (readback != i) {
- post_log ("Memory error at %08x, "
+ post_log("Memory error at %08x, "
"wrote %08x, read %08x !\n",
mem + i, i, readback);
break;
}
if (i % 1024 == 0)
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
}
return ret;
}
-static int memory_post_test4 (unsigned long start, unsigned long size)
+static int memory_post_test4(unsigned long start, unsigned long size)
{
unsigned long i;
ulong *mem = (ulong *) start;
for (i = 0; i < size / sizeof (ulong); i++) {
mem[i] = ~i;
if (i % 1024 == 0)
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
}
- for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
+ for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
readback = mem[i];
if (readback != ~i) {
- post_log ("Memory error at %08x, "
+ post_log("Memory error at %08x, "
"wrote %08x, read %08x !\n",
mem + i, ~i, readback);
break;
}
if (i % 1024 == 0)
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
}
return ret;
}
-static int memory_post_tests (unsigned long start, unsigned long size)
+static int memory_post_test_lines(unsigned long start, unsigned long size)
{
int ret = 0;
- if (ret == 0)
- ret = memory_post_dataline ((unsigned long long *)start);
- WATCHDOG_RESET ();
- if (ret == 0)
- ret = memory_post_addrline ((ulong *)start, (ulong *)start, size);
- WATCHDOG_RESET ();
- if (ret == 0)
- ret = memory_post_addrline ((ulong *)(start + size - 8),
- (ulong *)start, size);
- WATCHDOG_RESET ();
- if (ret == 0)
- ret = memory_post_test1 (start, size, 0x00000000);
- WATCHDOG_RESET ();
- if (ret == 0)
- ret = memory_post_test1 (start, size, 0xffffffff);
- WATCHDOG_RESET ();
- if (ret == 0)
- ret = memory_post_test1 (start, size, 0x55555555);
- WATCHDOG_RESET ();
- if (ret == 0)
- ret = memory_post_test1 (start, size, 0xaaaaaaaa);
- WATCHDOG_RESET ();
- if (ret == 0)
- ret = memory_post_test2 (start, size);
- WATCHDOG_RESET ();
- if (ret == 0)
- ret = memory_post_test3 (start, size);
- WATCHDOG_RESET ();
- if (ret == 0)
- ret = memory_post_test4 (start, size);
- WATCHDOG_RESET ();
+ ret = memory_post_dataline((unsigned long long *)start);
+ WATCHDOG_RESET();
+ if (!ret)
+ ret = memory_post_addrline((ulong *)start, (ulong *)start,
+ size);
+ WATCHDOG_RESET();
+ if (!ret)
+ ret = memory_post_addrline((ulong *)(start+size-8),
+ (ulong *)start, size);
+ WATCHDOG_RESET();
return ret;
}
+static int memory_post_test_patterns(unsigned long start, unsigned long size)
+{
+ int ret = 0;
+
+ ret = memory_post_test1(start, size, 0x00000000);
+ WATCHDOG_RESET();
+ if (!ret)
+ ret = memory_post_test1(start, size, 0xffffffff);
+ WATCHDOG_RESET();
+ if (!ret)
+ ret = memory_post_test1(start, size, 0x55555555);
+ WATCHDOG_RESET();
+ if (!ret)
+ ret = memory_post_test1(start, size, 0xaaaaaaaa);
+ WATCHDOG_RESET();
+ if (!ret)
+ ret = memory_post_test2(start, size);
+ WATCHDOG_RESET();
+ if (!ret)
+ ret = memory_post_test3(start, size);
+ WATCHDOG_RESET();
+ if (!ret)
+ ret = memory_post_test4(start, size);
+ WATCHDOG_RESET();
+
+ return ret;
+}
+
+static int memory_post_test_regions(unsigned long start, unsigned long size)
+{
+ unsigned long i;
+ int ret = 0;
+
+ for (i = 0; i < (size >> 20) && (!ret); i++) {
+ if (!ret)
+ ret = memory_post_test_patterns(i << 20, 0x800);
+ if (!ret)
+ ret = memory_post_test_patterns((i << 20) + 0xff800,
+ 0x800);
+ }
+
+ return ret;
+}
+
+static int memory_post_tests(unsigned long start, unsigned long size)
+{
+ int ret = 0;
+
+ ret = memory_post_test_lines(start, size);
+ if (!ret)
+ ret = memory_post_test_patterns(start, size);
+
+ return ret;
+}
+
+/*
+ * !! this is only valid, if you have contiguous memory banks !!
+ */
__attribute__((weak))
int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
bd_t *bd = gd->bd;
+
*vstart = CONFIG_SYS_SDRAM_BASE;
- *size = (bd->bi_memsize >= 256 << 20 ?
- 256 << 20 : bd->bi_memsize) - (1 << 20);
+ *size = (gd->ram_size >= 256 << 20 ?
+ 256 << 20 : gd->ram_size) - (1 << 20);
/* Limit area to be tested with the board info struct */
if ((*vstart) + (*size) > (ulong)bd)
return;
}
+int memory_regions_post_test(int flags)
+{
+ int ret = 0;
+ phys_addr_t phys_offset = 0;
+ u32 memsize, vstart;
+
+ arch_memory_test_prepare(&vstart, &memsize, &phys_offset);
+
+ ret = memory_post_test_lines(vstart, memsize);
+ if (!ret)
+ ret = memory_post_test_regions(vstart, memsize);
+
+ return ret;
+}
+
int memory_post_test(int flags)
{
int ret = 0;
if (flags & POST_SLOWTEST) {
ret = memory_post_tests(vstart, memsize);
} else { /* POST_NORMAL */
- unsigned long i;
- for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
- if (ret == 0)
- ret = memory_post_tests(i << 20, 0x800);
- if (ret == 0)
- ret = memory_post_tests(
- (i << 20) + 0xff800, 0x800);
- }
+ ret = memory_post_test_regions(vstart, memsize);
}
} while (!ret &&
!arch_memory_test_advance(&vstart, &memsize, &phys_offset));
return ret;
}
-#endif /* CONFIG_POST & CONFIG_SYS_POST_MEMORY */
+#endif /* CONFIG_POST&(CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) */