/*****************************************************************************/
/* */
-/* instr.h */
+/* instr.h */
/* */
-/* Instruction encoding for the ca65 macroassembler */
+/* Instruction encoding for the ca65 macroassembler */
/* */
/* */
/* */
-/* (C) 1998-2003 Ullrich von Bassewitz */
-/* Römerstrasse 52 */
-/* D-70794 Filderstadt */
-/* EMail: uz@cc65.org */
+/* (C) 1998-2012, Ullrich von Bassewitz */
+/* Roemerstrasse 52 */
+/* D-70794 Filderstadt */
+/* EMail: uz@cc65.org */
/* */
/* */
/* This software is provided 'as-is', without any expressed or implied */
/* common */
#include "cpu.h"
+#include "strbuf.h"
/*****************************************************************************/
-/* Data */
+/* Data for 6502 and successors */
/*****************************************************************************/
* When assembling for the 6502 or 65C02, all addressing modes that are not
* available on these CPUs are removed before doing any checks.
*/
-#define AM_IMPLICIT 0x00000003UL
-#define AM_ACCU 0x00000002UL
-#define AM_DIR 0x00000004UL
-#define AM_ABS 0x00000008UL
-#define AM_ABS_LONG 0x00000010UL
-#define AM_DIR_X 0x00000020UL
-#define AM_ABS_X 0x00000040UL
-#define AM_ABS_LONG_X 0x00000080UL
-#define AM_DIR_Y 0x00000100UL
-#define AM_ABS_Y 0x00000200UL
-#define AM_DIR_IND 0x00000400UL
-#define AM_ABS_IND 0x00000800UL
-#define AM_DIR_IND_LONG 0x00001000UL
-#define AM_DIR_IND_Y 0x00002000UL
-#define AM_DIR_IND_LONG_Y 0x00004000UL
-#define AM_DIR_X_IND 0x00008000UL
-#define AM_ABS_X_IND 0x00010000UL
-#define AM_REL 0x00020000UL
-#define AM_REL_LONG 0x00040000UL
-#define AM_STACK_REL 0x00080000UL
-#define AM_STACK_REL_IND_Y 0x00100000UL
-#define AM_IMM_ACCU 0x00200000UL
-#define AM_IMM_INDEX 0x00400000UL
-#define AM_IMM_IMPLICIT 0x00800000UL
-#define AM_IMM (AM_IMM_ACCU | AM_IMM_INDEX | AM_IMM_IMPLICIT)
-#define AM_BLOCKMOVE 0x01000000UL
+#define AM65_IMPLICIT 0x00000003UL
+#define AM65_ACCU 0x00000002UL
+#define AM65_DIR 0x00000004UL
+#define AM65_ABS 0x00000008UL
+#define AM65_ABS_LONG 0x00000010UL
+#define AM65_DIR_X 0x00000020UL
+#define AM65_ABS_X 0x00000040UL
+#define AM65_ABS_LONG_X 0x00000080UL
+#define AM65_DIR_Y 0x00000100UL
+#define AM65_ABS_Y 0x00000200UL
+#define AM65_DIR_IND 0x00000400UL
+#define AM65_ABS_IND 0x00000800UL
+#define AM65_DIR_IND_LONG 0x00001000UL
+#define AM65_DIR_IND_Y 0x00002000UL
+#define AM65_DIR_IND_LONG_Y 0x00004000UL
+#define AM65_DIR_X_IND 0x00008000UL
+#define AM65_ABS_X_IND 0x00010000UL
+#define AM65_REL 0x00020000UL
+#define AM65_REL_LONG 0x00040000UL
+#define AM65_STACK_REL 0x00080000UL
+#define AM65_STACK_REL_IND_Y 0x00100000UL
+#define AM65_IMM_ACCU 0x00200000UL
+#define AM65_IMM_INDEX 0x00400000UL
+#define AM65_IMM_IMPLICIT 0x00800000UL
+#define AM65_BLOCKMOVE 0x01000000UL
+#define AM65_BLOCKXFER 0x02000000UL
+#define AM65_ABS_IND_LONG 0x04000000UL
/* Bitmask for all ZP operations that have correspondent ABS ops */
-#define AM_ZP (AM_DIR | AM_DIR_X | AM_DIR_Y | AM_DIR_IND | AM_DIR_X_IND)
+#define AM65_SET_ZP (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND)
+
+/* Bitmask for all ABS operations that have correspondent FAR ops */
+#define AM65_SET_ABS (AM65_ABS | AM65_ABS_X)
+
+/* Bitmask for all ZP operations */
+#define AM65_ALL_ZP (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND)
+
+/* Bitmask for all ABS operations */
+#define AM65_ALL_ABS (AM65_ABS | AM65_ABS_X | AM65_ABS_Y | AM65_ABS_IND | AM65_ABS_X_IND)
+
+/* Bitmask for all FAR operations */
+#define AM65_ALL_FAR (AM65_ABS_LONG | AM65_ABS_LONG_X)
+
+/* Bitmask for all immediate operations */
+#define AM65_ALL_IMM (AM65_IMM_ACCU | AM65_IMM_INDEX | AM65_IMM_IMPLICIT)
/* Bit numbers and count */
-#define AMI_IMM_ACCU 21
-#define AMI_IMM_INDEX 22
-#define AMI_COUNT 25
+#define AM65I_IMM_ACCU 21
+#define AM65I_IMM_INDEX 22
+#define AM65I_IMM_IMPLICIT 23
+#define AM65I_COUNT 27
/* Description for one instruction */
typedef struct InsDesc InsDesc;
struct InsDesc {
- char Mnemonic [8];
- unsigned long AddrMode; /* Valid adressing modes */
- unsigned char BaseCode; /* Base opcode */
- unsigned char ExtCode; /* Number of ext code table */
- void (*Emit) (const InsDesc*);/* Handler function */
+ char Mnemonic[5];
+ unsigned long AddrMode; /* Valid adressing modes */
+ unsigned char BaseCode; /* Base opcode */
+ unsigned char ExtCode; /* Number of ext code table */
+ void (*Emit) (const InsDesc*);/* Handler function */
};
/* An instruction table */
typedef struct InsTable InsTable;
struct InsTable {
- unsigned Count; /* Number of intstructions */
- InsDesc Ins[1]; /* Varying length */
+ unsigned Count; /* Number of intstructions */
+ InsDesc Ins[1]; /* Varying length */
};
/* The instruction table for the currently active CPU */
extern const InsTable* InsTab;
-/* Table to build the effective opcode from a base opcode and an addressing
- * mode.
- */
-extern unsigned char EATab [9][AMI_COUNT];
-
/* Table that encodes the additional bytes for each instruction */
-extern unsigned char ExtBytes [AMI_COUNT];
+extern unsigned char ExtBytes[AM65I_COUNT];
/*****************************************************************************/
-/* Code */
+/* Data for the SWEET16 pseudo CPU */
+/*****************************************************************************/
+
+
+
+/* SWEET16 addressing modes */
+#define AMSW16_IMP 0x0001 /* Implicit */
+#define AMSW16_BRA 0x0002 /* A branch */
+#define AMSW16_IMM 0x0004 /* Immediate */
+#define AMSW16_IND 0x0008 /* Indirect */
+#define AMSW16_REG 0x0010 /* Register */
+
+#define AMSW16I_COUNT 5 /* Number of addressing modes */
+
+
+
+/*****************************************************************************/
+/* Code */
/*****************************************************************************/
cpu_t GetCPU (void);
/* Return the current CPU */
-int FindInstruction (const char* Ident);
+int FindInstruction (const StrBuf* Ident);
/* Check if Ident is a valid mnemonic. If so, return the index in the
* instruction table. If not, return -1.
*/
/* End of instr.h */
#endif
-
-
-
-
projects / cc65 / blobdiff