/* */
/* */
/* */
-/* (C) 2001-2003 Ullrich von Bassewitz */
-/* Römerstrasse 52 */
-/* D-70794 Filderstadt */
-/* EMail: uz@cc65.org */
+/* (C) 2001-2009, Ullrich von Bassewitz */
+/* Roemerstrasse 52 */
+/* D-70794 Filderstadt */
+/* EMail: uz@cc65.org */
/* */
/* */
/* This software is provided 'as-is', without any expressed or implied */
/* cc65 */
#include "codeent.h"
+#include "coptind.h"
#include "codeinfo.h"
#include "codeopt.h"
#include "error.h"
-#include "coptind.h"
+static int MemAccess (CodeSeg* S, unsigned From, unsigned To, const char* Arg)
+/* Checks a range of code entries if there are any memory accesses to Arg.
+ * Note: This function is not 100% safe, because there is more than one way
+ * to express a memory location ("foo" and "foo+0" comes to mind) and there
+ * may be other accesses through pointers. For the code generated by cc65 and
+ * for the purpose of the caller (OptPushPop) it is assumed to be safe enough
+ * however.
+ */
+{
+ /* Walk over all code entries */
+ while (From <= To) {
+
+ /* Get the next entry */
+ CodeEntry* E = CS_GetEntry (S, From);
+
+ /* For simplicity, we just check if there is an argument and if this
+ * argument equals Arg.
+ */
+ if (E->Arg && strcmp (E->Arg, Arg) == 0) {
+ /* Found an access */
+ return 1;
+ }
+
+ /* Next entry */
+ ++From;
+ }
+
+ /* Nothing found */
+ return 0;
+}
+
+
+
static int GetBranchDist (CodeSeg* S, unsigned From, CodeEntry* To)
/* Get the branch distance between the two entries and return it. The distance
* will be negative for backward jumps and positive for forward jumps.
/* Remember, we had changes */
++Changes;
- /* Done */
- continue;
-
- }
-
/* Check if both are conditional branches, and the condition of
* the second is the inverse of that of the first. In this case,
* the second branch will never be taken, and we may jump directly
* to the instruction behind this one.
*/
- if ((E->Info & OF_CBRA) != 0 && (N->Info & OF_CBRA) != 0) {
+ } else if ((E->Info & OF_CBRA) != 0 && (N->Info & OF_CBRA) != 0) {
CodeEntry* X; /* Instruction behind N */
CodeLabel* LX; /* Label attached to X */
/* Remember, we had changes */
++Changes;
-
- /* Done */
- continue;
-
}
}
-unsigned OptJumpTarget (CodeSeg* S)
+unsigned OptJumpTarget1 (CodeSeg* S)
/* If the instruction preceeding an unconditional branch is the same as the
* instruction preceeding the jump target, the jump target may be moved
* one entry back. This is a size optimization, since the instruction before
/* Check if we have a jump or branch, and a matching label, which
* is not attached to the jump itself
*/
- if (E2 != 0 &&
+ if (E2 != 0 &&
(E2->Info & OF_UBRA) != 0 &&
- E2->JumpTo &&
+ E2->JumpTo &&
E2->JumpTo->Owner != E2) {
/* Get the entry preceeding the branch target */
/* Check if both preceeding instructions are identical */
if (!CodeEntriesAreEqual (E1, T1)) {
/* Not equal, try next */
- goto NextEntry;
+ goto NextEntry;
}
/* Get the label for the instruction preceeding the jump target.
/* Remember, we had changes */
++Changes;
- }
-
+ } else {
NextEntry:
- /* Next entry */
- ++I;
+ /* Next entry */
+ ++I;
+ }
+ }
+
+ /* Return the number of changes made */
+ return Changes;
+}
+
+
+
+unsigned OptJumpTarget2 (CodeSeg* S)
+/* If a bcs jumps to a sec insn or a bcc jumps to clc, skip this insn, since
+ * it's job is already done.
+ */
+{
+ unsigned Changes = 0;
+
+ /* Walk over the entries */
+ unsigned I = 0;
+ while (I < CS_GetEntryCount (S)) {
+
+ /* OP that may be skipped */
+ opc_t OPC;
+ /* Jump target insn, old and new */
+ CodeEntry* T;
+ CodeEntry* N;
+
+ /* New jump label */
+ CodeLabel* L;
+
+ /* Get next entry */
+ CodeEntry* E = CS_GetEntry (S, I);
+
+ /* Check if this is a bcc insn */
+ if (E->OPC == OP65_BCC || E->OPC == OP65_JCC) {
+ OPC = OP65_CLC;
+ } else if (E->OPC == OP65_BCS || E->OPC == OP65_JCS) {
+ OPC = OP65_SEC;
+ } else {
+ /* Not what we're looking for */
+ goto NextEntry;
+ }
+
+ /* Must have a jump target */
+ if (E->JumpTo == 0) {
+ goto NextEntry;
+ }
+
+ /* Get the owner insn of the jump target and check if it's the one, we
+ * will skip if present.
+ */
+ T = E->JumpTo->Owner;
+ if (T->OPC != OPC) {
+ goto NextEntry;
+ }
+
+ /* Get the entry following the branch target */
+ N = CS_GetNextEntry (S, CS_GetEntryIndex (S, T));
+ if (N == 0) {
+ /* There is no such entry */
+ goto NextEntry;
+ }
+
+ /* Get the label for the instruction following the jump target.
+ * This routine will create a new label if the instruction does
+ * not already have one.
+ */
+ L = CS_GenLabel (S, N);
+
+ /* Change the jump target to point to this new label */
+ CS_MoveLabelRef (S, E, L);
+
+ /* Remember that we had changes */
+ ++Changes;
+
+NextEntry:
+ /* Next entry */
+ ++I;
}
/* Return the number of changes made */
-unsigned OptCondBranches (CodeSeg* S)
+unsigned OptCondBranches1 (CodeSeg* S)
/* Performs several optimization steps:
*
* - If an immidiate load of a register is followed by a conditional jump that
CS_DelEntry (S, I+1);
/* Remember, we had changes */
- ++Changes;
+ ++Changes;
} else if ((BC == BC_EQ && E->Num == 0) ||
(BC == BC_NE && E->Num != 0) ||
}
if ((E->Info & OF_CBRA) != 0 && /* It's a conditional branch */
- (L = E->JumpTo) != 0 && /* ..referencing a local label */
+ (L = E->JumpTo) != 0 && /* ..referencing a local label */
(N = CS_GetNextEntry (S, I)) != 0 && /* There is a following entry */
(N->Info & OF_UBRA) != 0 && /* ..which is an uncond branch, */
!CE_HasLabel (N) && /* ..has no label attached */
+unsigned OptCondBranches2 (CodeSeg* S)
+/* If on entry to a "rol a" instruction the accu is zero, and a beq/bne follows,
+ * we can remove the rol and branch on the state of the carry flag.
+ */
+{
+ unsigned Changes = 0;
+ unsigned I;
+
+ /* Generate register info for this step */
+ CS_GenRegInfo (S);
+
+ /* Walk over the entries */
+ I = 0;
+ while (I < CS_GetEntryCount (S)) {
+
+ CodeEntry* N;
+
+ /* Get next entry */
+ CodeEntry* E = CS_GetEntry (S, I);
+
+ /* Check if it's a rol insn with A in accu and a branch follows */
+ if (E->OPC == OP65_ROL &&
+ E->AM == AM65_ACC &&
+ E->RI->In.RegA == 0 &&
+ !CE_HasLabel (E) &&
+ (N = CS_GetNextEntry (S, I)) != 0 &&
+ (N->Info & OF_ZBRA) != 0 &&
+ !RegAUsed (S, I+1)) {
+
+ /* Replace the branch condition */
+ switch (GetBranchCond (N->OPC)) {
+ case BC_EQ: CE_ReplaceOPC (N, OP65_JCC); break;
+ case BC_NE: CE_ReplaceOPC (N, OP65_JCS); break;
+ default: Internal ("Unknown branch condition in OptCondBranches2");
+ }
+
+ /* Delete the rol insn */
+ CS_DelEntry (S, I);
+
+ /* Remember, we had changes */
+ ++Changes;
+ }
+
+ /* Next entry */
+ ++I;
+ }
+
+ /* Free register info */
+ CS_FreeRegInfo (S);
+
+ /* Return the number of changes made */
+ return Changes;
+}
+
+
+
/*****************************************************************************/
/* Remove unused loads and stores */
/*****************************************************************************/
/* Check which sort of load or transfer it is */
unsigned R;
switch (E->OPC) {
- case OP65_DEA:
- case OP65_INA:
- case OP65_LDA:
+ case OP65_DEA:
+ case OP65_INA:
+ case OP65_LDA:
case OP65_TXA:
case OP65_TYA: R = REG_A; break;
- case OP65_DEX:
- case OP65_INX:
- case OP65_LDX:
+ case OP65_DEX:
+ case OP65_INX:
+ case OP65_LDX:
case OP65_TAX: R = REG_X; break;
- case OP65_DEY:
- case OP65_INY:
+ case OP65_DEY:
+ case OP65_INY:
case OP65_LDY:
case OP65_TAY: R = REG_Y; break;
default: goto NextEntry; /* OOPS */
if ((GetRegInfo (S, I+1, R) & R) == 0) {
/* Register value is not used, remove the load */
- CS_DelEntry (S, I);
+ CS_DelEntry (S, I);
- /* Remember, we had changes */
- ++Changes;
+ /* Remember, we had changes. Account the deleted entry in I. */
+ ++Changes;
+ --I;
}
}
/* Remember, we had changes */
++Changes;
+ /* Continue with next insn */
+ continue;
}
}
case OP65_LDA:
if (RegValIsKnown (In->RegA) && /* Value of A is known */
- CE_KnownImm (E) && /* Value to be loaded is known */
- In->RegA == (long) E->Num && /* Both are equal */
+ CE_IsKnownImm (E, In->RegA) && /* Value to be loaded is known */
(N = CS_GetNextEntry (S, I)) != 0 && /* There is a next entry */
!CE_UseLoadFlags (N)) { /* Which does not use the flags */
Delete = 1;
case OP65_LDX:
if (RegValIsKnown (In->RegX) && /* Value of X is known */
- CE_KnownImm (E) && /* Value to be loaded is known */
- In->RegX == (long) E->Num && /* Both are equal */
+ CE_IsKnownImm (E, In->RegX) && /* Value to be loaded is known */
(N = CS_GetNextEntry (S, I)) != 0 && /* There is a next entry */
!CE_UseLoadFlags (N)) { /* Which does not use the flags */
Delete = 1;
case OP65_LDY:
if (RegValIsKnown (In->RegY) && /* Value of Y is known */
- CE_KnownImm (E) && /* Value to be loaded is known */
- In->RegY == (long) E->Num && /* Both are equal */
+ CE_IsKnownImm (E, In->RegY) && /* Value to be loaded is known */
(N = CS_GetNextEntry (S, I)) != 0 && /* There is a next entry */
!CE_UseLoadFlags (N)) { /* Which does not use the flags */
Delete = 1;
* remove the store.
*/
if (RegValIsKnown (In->RegA) && /* Value of A is known */
- E->AM == AM65_ZP && /* Store into zp */
+ E->AM == AM65_ZP && /* Store into zp */
In->RegA == ZPRegVal (E->Chg, In)) { /* Value identical */
Delete = 1;
*/
} else if (RegValIsKnown (In->RegY)) {
if (In->RegY == In->RegA) {
- CE_ReplaceOPC (E, OP65_STA);
+ CE_ReplaceOPC (E, OP65_STA);
} else if (In->RegY == In->RegX &&
E->AM != AM65_ABSX &&
E->AM != AM65_ZPX) {
* location does already contain the value to be stored,
* remove the store.
*/
- if (CPU >= CPU_65C02 && E->AM == AM65_ZP) {
+ if ((CPUIsets[CPU] & CPU_ISET_65SC02) != 0 && E->AM == AM65_ZP) {
if (ZPRegVal (E->Chg, In) == 0) {
Delete = 1;
}
case OP65_TYA:
if (RegValIsKnown (In->RegY) &&
- In->RegY == In->RegA &&
+ In->RegY == In->RegA &&
(N = CS_GetNextEntry (S, I)) != 0 &&
!CE_UseLoadFlags (N)) {
/* Value is identical and not followed by a branch */
unsigned I = 0;
while (I < CS_GetEntryCount (S)) {
- CodeEntry* N;
- CodeEntry* X;
+ CodeEntry* N;
+ CodeEntry* X;
- /* Get next entry */
+ /* Get next entry */
CodeEntry* E = CS_GetEntry (S, I);
/* Check if it is a store instruction followed by a load from the
if (I == 0) {
/* No preceeding entry */
goto NextEntry;
- }
+ }
P = CS_GetEntry (S, I-1);
if ((P->Info & OF_SETF) == 0) {
/* Does not set the flags */
+unsigned OptTransfers3 (CodeSeg* S)
+/* Replace a register transfer followed by a store of the second register by a
+ * store of the first register if this is possible.
+ */
+{
+ unsigned Changes = 0;
+ unsigned UsedRegs = REG_NONE; /* Track used registers */
+ unsigned Xfer = 0; /* Index of transfer insn */
+ unsigned Store = 0; /* Index of store insn */
+ CodeEntry* XferEntry = 0; /* Pointer to xfer insn */
+ CodeEntry* StoreEntry = 0; /* Pointer to store insn */
+
+ enum {
+ Initialize,
+ Search,
+ FoundXfer,
+ FoundStore
+ } State = Initialize;
+
+ /* Walk over the entries. Look for a xfer instruction that is followed by
+ * a store later, where the value of the register is not used later.
+ */
+ unsigned I = 0;
+ while (I < CS_GetEntryCount (S)) {
+
+ /* Get next entry */
+ CodeEntry* E = CS_GetEntry (S, I);
+
+ switch (State) {
+
+ case Initialize:
+ /* Clear the list of used registers */
+ UsedRegs = REG_NONE;
+ /* FALLTHROUGH */
+
+ case Search:
+ if (E->Info & OF_XFR) {
+ /* Found start of sequence */
+ Xfer = I;
+ XferEntry = E;
+ State = FoundXfer;
+ }
+ break;
+
+ case FoundXfer:
+ /* If we find a conditional jump, abort the sequence, since
+ * handling them makes things really complicated.
+ */
+ if (E->Info & OF_CBRA) {
+
+ /* Switch back to searching */
+ I = Xfer;
+ State = Initialize;
+
+ /* Does this insn use the target register of the transfer? */
+ } else if ((E->Use & XferEntry->Chg) != 0) {
+
+ /* It it's a store instruction, and the block is a basic
+ * block, proceed. Otherwise restart
+ */
+ if ((E->Info & OF_STORE) != 0 &&
+ CS_IsBasicBlock (S, Xfer, I)) {
+ Store = I;
+ StoreEntry = E;
+ State = FoundStore;
+ } else {
+ I = Xfer;
+ State = Initialize;
+ }
+
+ /* Does this insn change the target register of the transfer? */
+ } else if (E->Chg & XferEntry->Chg) {
+
+ /* We *may* add code here to remove the transfer, but I'm
+ * currently not sure about the consequences, so I won't
+ * do that and bail out instead.
+ */
+ I = Xfer;
+ State = Initialize;
+
+ /* Does this insn have a label? */
+ } else if (CE_HasLabel (E)) {
+
+ /* Too complex to handle - bail out */
+ I = Xfer;
+ State = Initialize;
+
+ } else {
+ /* Track used registers */
+ UsedRegs |= E->Use;
+ }
+ break;
+
+ case FoundStore:
+ /* We are at the instruction behind the store. If the register
+ * isn't used later, and we have an address mode match, we can
+ * replace the transfer by a store and remove the store here.
+ */
+ if ((GetRegInfo (S, I, XferEntry->Chg) & XferEntry->Chg) == 0 &&
+ (StoreEntry->AM == AM65_ABS ||
+ StoreEntry->AM == AM65_ZP) &&
+ (StoreEntry->AM != AM65_ZP ||
+ (StoreEntry->Chg & UsedRegs) == 0) &&
+ !MemAccess (S, Xfer+1, Store-1, StoreEntry->Arg)) {
+
+ /* Generate the replacement store insn */
+ CodeEntry* X = 0;
+ switch (XferEntry->OPC) {
+
+ case OP65_TXA:
+ X = NewCodeEntry (OP65_STX,
+ StoreEntry->AM,
+ StoreEntry->Arg,
+ 0,
+ StoreEntry->LI);
+ break;
+
+ case OP65_TAX:
+ X = NewCodeEntry (OP65_STA,
+ StoreEntry->AM,
+ StoreEntry->Arg,
+ 0,
+ StoreEntry->LI);
+ break;
+
+ case OP65_TYA:
+ X = NewCodeEntry (OP65_STY,
+ StoreEntry->AM,
+ StoreEntry->Arg,
+ 0,
+ StoreEntry->LI);
+ break;
+
+ case OP65_TAY:
+ X = NewCodeEntry (OP65_STA,
+ StoreEntry->AM,
+ StoreEntry->Arg,
+ 0,
+ StoreEntry->LI);
+ break;
+
+ default:
+ break;
+ }
+
+ /* If we have a replacement store, change the code */
+ if (X) {
+ /* Insert after the xfer insn */
+ CS_InsertEntry (S, X, Xfer+1);
+
+ /* Remove the xfer instead */
+ CS_DelEntry (S, Xfer);
+
+ /* Remove the final store */
+ CS_DelEntry (S, Store);
+
+ /* Correct I so we continue with the next insn */
+ I -= 2;
+
+ /* Remember we had changes */
+ ++Changes;
+ } else {
+ /* Restart after last xfer insn */
+ I = Xfer;
+ }
+ } else {
+ /* Restart after last xfer insn */
+ I = Xfer;
+ }
+ State = Initialize;
+ break;
+
+ }
+
+ /* Next entry */
+ ++I;
+ }
+
+ /* Return the number of changes made */
+ return Changes;
+}
+
+
+
+unsigned OptTransfers4 (CodeSeg* S)
+/* Replace a load of a register followed by a transfer insn of the same register
+ * by a load of the second register if possible.
+ */
+{
+ unsigned Changes = 0;
+ unsigned Load = 0; /* Index of load insn */
+ unsigned Xfer = 0; /* Index of transfer insn */
+ CodeEntry* LoadEntry = 0; /* Pointer to load insn */
+ CodeEntry* XferEntry = 0; /* Pointer to xfer insn */
+
+ enum {
+ Search,
+ FoundLoad,
+ FoundXfer
+ } State = Search;
+
+ /* Walk over the entries. Look for a load instruction that is followed by
+ * a load later.
+ */
+ unsigned I = 0;
+ while (I < CS_GetEntryCount (S)) {
+
+ /* Get next entry */
+ CodeEntry* E = CS_GetEntry (S, I);
+
+ switch (State) {
+
+ case Search:
+ if (E->Info & OF_LOAD) {
+ /* Found start of sequence */
+ Load = I;
+ LoadEntry = E;
+ State = FoundLoad;
+ }
+ break;
+
+ case FoundLoad:
+ /* If we find a conditional jump, abort the sequence, since
+ * handling them makes things really complicated.
+ */
+ if (E->Info & OF_CBRA) {
+
+ /* Switch back to searching */
+ I = Load;
+ State = Search;
+
+ /* Does this insn use the target register of the load? */
+ } else if ((E->Use & LoadEntry->Chg) != 0) {
+
+ /* It it's a xfer instruction, and the block is a basic
+ * block, proceed. Otherwise restart
+ */
+ if ((E->Info & OF_XFR) != 0 &&
+ CS_IsBasicBlock (S, Load, I)) {
+ Xfer = I;
+ XferEntry = E;
+ State = FoundXfer;
+ } else {
+ I = Load;
+ State = Search;
+ }
+
+ /* Does this insn change the target register of the load? */
+ } else if (E->Chg & LoadEntry->Chg) {
+
+ /* We *may* add code here to remove the load, but I'm
+ * currently not sure about the consequences, so I won't
+ * do that and bail out instead.
+ */
+ I = Load;
+ State = Search;
+ }
+ break;
+
+ case FoundXfer:
+ /* We are at the instruction behind the xfer. If the register
+ * isn't used later, and we have an address mode match, we can
+ * replace the transfer by a load and remove the initial load.
+ */
+ if ((GetRegInfo (S, I, LoadEntry->Chg) & LoadEntry->Chg) == 0 &&
+ (LoadEntry->AM == AM65_ABS ||
+ LoadEntry->AM == AM65_ZP ||
+ LoadEntry->AM == AM65_IMM) &&
+ !MemAccess (S, Load+1, Xfer-1, LoadEntry->Arg)) {
+
+ /* Generate the replacement load insn */
+ CodeEntry* X = 0;
+ switch (XferEntry->OPC) {
+
+ case OP65_TXA:
+ case OP65_TYA:
+ X = NewCodeEntry (OP65_LDA,
+ LoadEntry->AM,
+ LoadEntry->Arg,
+ 0,
+ LoadEntry->LI);
+ break;
+
+ case OP65_TAX:
+ X = NewCodeEntry (OP65_LDX,
+ LoadEntry->AM,
+ LoadEntry->Arg,
+ 0,
+ LoadEntry->LI);
+ break;
+
+ case OP65_TAY:
+ X = NewCodeEntry (OP65_LDY,
+ LoadEntry->AM,
+ LoadEntry->Arg,
+ 0,
+ LoadEntry->LI);
+ break;
+
+ default:
+ break;
+ }
+
+ /* If we have a replacement load, change the code */
+ if (X) {
+ /* Insert after the xfer insn */
+ CS_InsertEntry (S, X, Xfer+1);
+
+ /* Remove the xfer instead */
+ CS_DelEntry (S, Xfer);
+
+ /* Remove the initial load */
+ CS_DelEntry (S, Load);
+
+ /* Correct I so we continue with the next insn */
+ I -= 2;
+
+ /* Remember we had changes */
+ ++Changes;
+ } else {
+ /* Restart after last xfer insn */
+ I = Xfer;
+ }
+ } else {
+ /* Restart after last xfer insn */
+ I = Xfer;
+ }
+ State = Search;
+ break;
+
+ }
+
+ /* Next entry */
+ ++I;
+ }
+
+ /* Return the number of changes made */
+ return Changes;
+}
+
+
+
unsigned OptPushPop (CodeSeg* S)
/* Remove a PHA/PLA sequence were A is not used later */
{
unsigned I = 0;
while (I < CS_GetEntryCount (S)) {
+ CodeEntry* X;
+
/* Get next entry */
CodeEntry* E = CS_GetEntry (S, I);
} else if (E->OPC == OP65_PLA) {
/* Found a matching pop */
Pop = I;
- State = FoundPop;
+ /* Check that the block between Push and Pop is a basic
+ * block (one entry, one exit). Otherwise ignore it.
+ */
+ if (CS_IsBasicBlock (S, Push, Pop)) {
+ State = FoundPop;
+ } else {
+ /* Go into searching mode again */
+ State = Searching;
+ }
}
break;
case FoundPop:
- /* Next insn, just check if it is no conditional branch and
- * that A is not used later. Check also that the range we have
- * found now is a basic block, which means that the PHA is the
- * only entrance and the PLA the only exit.
+ /* We're at the instruction after the PLA.
+ * Check for the following conditions:
+ * - If this instruction is a store of A, and A is not used
+ * later, we may replace the PHA by the store and remove
+ * pla if several other conditions are met.
+ * - If this instruction is not a conditional branch, and A
+ * is unused later, we may remove PHA and PLA.
*/
- if ((E->Info & OF_CBRA) == 0 &&
- !RegAUsed (S, I) &&
- CS_IsBasicBlock (S, Push, Pop)) {
+ if (E->OPC == OP65_STA &&
+ !RegAUsed (S, I+1) &&
+ !MemAccess (S, Push+1, Pop-1, E->Arg)) {
+
+ /* Insert a STA after the PHA */
+ X = NewCodeEntry (E->OPC, E->AM, E->Arg, E->JumpTo, E->LI);
+ CS_InsertEntry (S, X, Push+1);
+
+ /* Remove the PHA instead */
+ CS_DelEntry (S, Push);
+
+ /* Remove the PLA/STA sequence */
+ CS_DelEntries (S, Pop, 2);
+
+ /* Correct I so we continue with the next insn */
+ I -= 2;
+
+ /* Remember we had changes */
+ ++Changes;
+
+ } else if ((E->Info & OF_CBRA) == 0 &&
+ !RegAUsed (S, I)) {
+
/* We can remove the PHA and PLA instructions */
CS_DelEntry (S, Pop);
CS_DelEntry (S, Push);
+
/* Correct I so we continue with the next insn */
I -= 2;
+
/* Remember we had changes */
++Changes;
+
}
/* Go into search mode again */
State = Searching;
/* Get next entry */
CodeEntry* E = CS_GetEntry (S, I);
- /* Get a pointer to the output registers of the insn */
+ /* Get pointers to the input and output registers of the insn */
const RegContents* Out = &E->RI->Out;
+ const RegContents* In = &E->RI->In;
+
+ /* Argument for LDn and flag */
+ const char* Arg = 0;
+ opc_t OPC = OP65_LDA;
/* Handle the different instructions */
switch (E->OPC) {
- case OP65_AND:
+ case OP65_LDA:
+ if (E->AM != AM65_IMM && RegValIsKnown (Out->RegA)) {
+ /* Result of load is known */
+ Arg = MakeHexArg (Out->RegA);
+ }
+ break;
+
+ case OP65_LDX:
+ if (E->AM != AM65_IMM && RegValIsKnown (Out->RegX)) {
+ /* Result of load is known but register is X */
+ Arg = MakeHexArg (Out->RegX);
+ OPC = OP65_LDX;
+ }
+ break;
+
+ case OP65_LDY:
+ if (E->AM != AM65_IMM && RegValIsKnown (Out->RegY)) {
+ /* Result of load is known but register is Y */
+ Arg = MakeHexArg (Out->RegY);
+ OPC = OP65_LDY;
+ }
+ break;
+
+ case OP65_ASL:
case OP65_EOR:
- case OP65_ORA:
+ case OP65_LSR:
if (RegValIsKnown (Out->RegA)) {
+ /* Accu op zp with known contents */
+ Arg = MakeHexArg (Out->RegA);
+ }
+ break;
+
+ case OP65_ADC:
+ case OP65_SBC:
+ /* If this is an operation with an immediate operand of zero,
+ * and the register is zero, the operation won't give us any
+ * results we don't already have (including the flags), so
+ * remove it. Something like this is generated as a result of
+ * a compare where parts of the values are known to be zero.
+ */
+ if (In->RegA == 0 && CE_IsKnownImm (E, 0x00)) {
+ /* 0-0 or 0+0 -> remove */
+ CS_DelEntry (S, I);
+ ++Changes;
+ } else if (RegValIsKnown (Out->RegA)) {
+ /* Accu op zp with known contents */
+ Arg = MakeHexArg (Out->RegA);
+ }
+ break;
+
+ case OP65_AND:
+ if (CE_IsKnownImm (E, 0xFF)) {
+ /* AND with 0xFF, remove */
+ CS_DelEntry (S, I);
+ ++Changes;
+ } else if (CE_IsKnownImm (E, 0x00)) {
+ /* AND with 0x00, replace by lda #$00 */
+ Arg = MakeHexArg (0x00);
+ } else if (RegValIsKnown (Out->RegA)) {
/* Accu AND zp with known contents */
- const char* Arg = MakeHexArg (Out->RegA);
- CodeEntry* X = NewCodeEntry (OP65_LDA, AM65_IMM, Arg, 0, E->LI);
- CS_InsertEntry (S, X, I+1);
+ Arg = MakeHexArg (Out->RegA);
+ } else if (In->RegA == 0xFF) {
+ /* AND but A contains 0xFF - replace by lda */
+ CE_ReplaceOPC (E, OP65_LDA);
+ ++Changes;
+ }
+ break;
+
+ case OP65_ORA:
+ if (CE_IsKnownImm (E, 0x00)) {
+ /* ORA with zero, remove */
CS_DelEntry (S, I);
++Changes;
+ } else if (CE_IsKnownImm (E, 0xFF)) {
+ /* ORA with 0xFF, replace by lda #$ff */
+ Arg = MakeHexArg (0xFF);
+ } else if (RegValIsKnown (Out->RegA)) {
+ /* Accu AND zp with known contents */
+ Arg = MakeHexArg (Out->RegA);
+ } else if (In->RegA == 0) {
+ /* ORA but A contains 0x00 - replace by lda */
+ CE_ReplaceOPC (E, OP65_LDA);
+ ++Changes;
}
break;
}
+ /* Check if we have to replace the insn by LDA */
+ if (Arg) {
+ CodeEntry* X = NewCodeEntry (OPC, AM65_IMM, Arg, 0, E->LI);
+ CS_InsertEntry (S, X, I+1);
+ CS_DelEntry (S, I);
+ ++Changes;
+ }
+
/* Next entry */
++I;
}
}
- } else if (CPU == CPU_65C02 &&
- (E->Info & OF_UBRA) != 0 &&
- E->JumpTo != 0 &&
+ } else if ((CPUIsets[CPU] & CPU_ISET_65SC02) != 0 &&
+ (E->Info & OF_UBRA) != 0 &&
+ E->JumpTo != 0 &&
IsShortDist (GetBranchDist (S, I, E->JumpTo->Owner))) {
/* The jump is short and may be replaced by a BRA on the 65C02 CPU */
+/*****************************************************************************/
+/* Optimize indirect loads */
+/*****************************************************************************/
+
+
+
+unsigned OptIndLoads1 (CodeSeg* S)
+/* Change
+ *
+ * lda (zp),y
+ *
+ * into
+ *
+ * lda (zp,x)
+ *
+ * provided that x and y are both zero.
+ */
+{
+ unsigned Changes = 0;
+ unsigned I;
+
+ /* Generate register info for this step */
+ CS_GenRegInfo (S);
+
+ /* Walk over the entries */
+ I = 0;
+ while (I < CS_GetEntryCount (S)) {
+
+ /* Get next entry */
+ CodeEntry* E = CS_GetEntry (S, I);
+
+ /* Check if it's what we're looking for */
+ if (E->OPC == OP65_LDA &&
+ E->AM == AM65_ZP_INDY &&
+ E->RI->In.RegY == 0 &&
+ E->RI->In.RegX == 0) {
+
+ /* Replace by the same insn with other addressing mode */
+ CodeEntry* X = NewCodeEntry (E->OPC, AM65_ZPX_IND, E->Arg, 0, E->LI);
+ CS_InsertEntry (S, X, I+1);
+
+ /* Remove the old insn */
+ CS_DelEntry (S, I);
+ ++Changes;
+ }
+
+ /* Next entry */
+ ++I;
+
+ }
+
+ /* Free register info */
+ CS_FreeRegInfo (S);
+
+ /* Return the number of changes made */
+ return Changes;
+}
+
+
+
+unsigned OptIndLoads2 (CodeSeg* S)
+/* Change
+ *
+ * lda (zp,x)
+ *
+ * into
+ *
+ * lda (zp),y
+ *
+ * provided that x and y are both zero.
+ */
+{
+ unsigned Changes = 0;
+ unsigned I;
+
+ /* Generate register info for this step */
+ CS_GenRegInfo (S);
+
+ /* Walk over the entries */
+ I = 0;
+ while (I < CS_GetEntryCount (S)) {
+
+ /* Get next entry */
+ CodeEntry* E = CS_GetEntry (S, I);
+
+ /* Check if it's what we're looking for */
+ if (E->OPC == OP65_LDA &&
+ E->AM == AM65_ZPX_IND &&
+ E->RI->In.RegY == 0 &&
+ E->RI->In.RegX == 0) {
+
+ /* Replace by the same insn with other addressing mode */
+ CodeEntry* X = NewCodeEntry (E->OPC, AM65_ZP_INDY, E->Arg, 0, E->LI);
+ CS_InsertEntry (S, X, I+1);
+
+ /* Remove the old insn */
+ CS_DelEntry (S, I);
+ ++Changes;
+ }
+
+ /* Next entry */
+ ++I;
+
+ }
+
+ /* Free register info */
+ CS_FreeRegInfo (S);
+
+ /* Return the number of changes made */
+ return Changes;
+}
+
+
+
projects / cc65 / blobdiff