#include "config.h"
#endif
-#include "replacements.h"
-
#include "cfi.h"
#include "non_cfi.h"
-
-#include "flash.h"
-#include "target.h"
-#include "log.h"
#include "armv4_5.h"
-#include "algorithm.h"
#include "binarybuffer.h"
-#include "types.h"
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
static int cfi_register_commands(struct command_context_s *cmd_ctx);
static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
}
/* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
-__inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
+static __inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
{
+ cfi_flash_bank_t *cfi_info = bank->driver_priv;
+
+ if(cfi_info->x16_as_x8) offset*=2;
+
/* while the sector list isn't built, only accesses to sector 0 work */
if (sector == 0)
return bank->base + offset * bank->bus_width;
target_t *target = bank->target;
u8 data[CFI_MAX_BUS_WIDTH];
- target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
+ target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
return data[0];
u8 data[CFI_MAX_BUS_WIDTH];
int i;
- target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
+ target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
{
static u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
{
target_t *target = bank->target;
+ cfi_flash_bank_t *cfi_info = bank->driver_priv;
u8 data[CFI_MAX_BUS_WIDTH * 2];
- target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
+ if(cfi_info->x16_as_x8)
+ {
+ u8 i;
+ for(i=0;i<2;i++)
+ target_read_memory(target, flash_address(bank, sector, offset+i), bank->bus_width, 1,
+ &data[i*bank->bus_width] );
+ }
+ else
+ target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
return data[0] | data[bank->bus_width] << 8;
static u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
{
target_t *target = bank->target;
+ cfi_flash_bank_t *cfi_info = bank->driver_priv;
u8 data[CFI_MAX_BUS_WIDTH * 4];
- target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
+ if(cfi_info->x16_as_x8)
+ {
+ u8 i;
+ for(i=0;i<4;i++)
+ target_read_memory(target, flash_address(bank, sector, offset+i), bank->bus_width, 1,
+ &data[i*bank->bus_width] );
+ }
+ else
+ target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
}
cfi_command(bank, 0x50, command);
- target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}
u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
{
cfi_command(bank, 0xf0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xff, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
{
cfi_command(bank, 0xf0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
{
cfi_command(bank, 0xf0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
for (i = first; i <= last; i++)
{
cfi_command(bank, 0x20, command);
- if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xd0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
else
{
cfi_command(bank, 0xff, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
}
cfi_command(bank, 0xff, command);
- return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}
for (i = first; i <= last; i++)
{
cfi_command(bank, 0xaa, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x55, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x80, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xaa, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x55, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x30, command);
- if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
else
{
cfi_command(bank, 0xf0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
}
cfi_command(bank, 0xf0, command);
- return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}
static int cfi_erase(struct flash_bank_s *bank, int first, int last)
{
cfi_command(bank, 0x60, command);
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
- if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
{
cfi_command(bank, 0x01, command);
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
- if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
{
cfi_command(bank, 0xd0, command);
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
- if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
u8 block_status;
/* read block lock bit, to verify status */
cfi_command(bank, 0x90, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
{
LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
cfi_command(bank, 0x70, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_intel_clear_status_register(bank);
cfi_command(bank, 0x60, command);
- if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x01, command);
- if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
}
cfi_command(bank, 0xff, command);
- return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}
static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
LOG_INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );
/* Execute algorithm, assume breakpoint for last instruction */
- retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params,
+ retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
cfi_info->write_algorithm->address,
cfi_info->write_algorithm->address + target_code_size - sizeof(u32),
10000, /* 10s should be enough for max. 32k of data */
buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
- retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params,
+ retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
cfi_info->write_algorithm->address,
cfi_info->write_algorithm->address + ((24 * 4) - 4),
10000, &armv4_5_info);
cfi_intel_clear_status_register(bank);
cfi_command(bank, 0x40, command);
- if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
- if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
{
return retval;
}
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
{
cfi_command(bank, 0xff, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
/* Initiate buffer operation _*/
cfi_command(bank, 0xE8, command);
- if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
{
cfi_command(bank, 0xff, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
/* Write buffer wordcount-1 and data words */
cfi_command(bank, bufferwsize-1, command);
- if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
- if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
{
return retval;
}
/* Commit write operation */
cfi_command(bank, 0xd0, command);
- if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
{
cfi_command(bank, 0xff, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
u8 command[8];
cfi_command(bank, 0xaa, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x55, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xa0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
- if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
{
return retval;
}
if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
{
cfi_command(bank, 0xf0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
// Unlock
cfi_command(bank, 0xaa, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x55, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
// Buffer load command
cfi_command(bank, 0x25, command);
- if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
/* Write buffer wordcount-1 and data words */
cfi_command(bank, bufferwsize-1, command);
- if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
- if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
{
return retval;
}
/* Commit write operation */
cfi_command(bank, 0x29, command);
- if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
{
cfi_command(bank, 0xf0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
for (i = 0; i < align; ++i, ++copy_p)
{
u8 byte;
- if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
+ if((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
{
return retval;
}
for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
{
u8 byte;
- if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
+ if((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
{
return retval;
}
/* return to read array mode, so we can read from flash again for padding */
cfi_command(bank, 0xf0, current_word);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xff, current_word);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
{
return retval;
}
for (; i < bank->bus_width; ++i, ++copy_p)
{
u8 byte;
- if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
+ if((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
{
return retval;
}
/* return to read array mode */
cfi_command(bank, 0xf0, current_word);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xff, current_word);
- return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
+ return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
}
static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
/* switch to read identifier codes mode ("AUTOSELECT") */
cfi_command(bank, 0xaa, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x55, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x90, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
if (bank->chip_width == 1)
{
u8 manufacturer, device_id;
- if((retval = target_read_u8(target, bank->base + 0x0, &manufacturer)) != ERROR_OK)
+ if((retval = target_read_u8(target, flash_address(bank, 0, 0x00), &manufacturer)) != ERROR_OK)
{
return retval;
}
- if((retval = target_read_u8(target, bank->base + 0x1, &device_id)) != ERROR_OK)
+ if((retval = target_read_u8(target, flash_address(bank, 0, 0x01), &device_id)) != ERROR_OK)
{
return retval;
}
}
else if (bank->chip_width == 2)
{
- if((retval = target_read_u16(target, bank->base + 0x0, &cfi_info->manufacturer)) != ERROR_OK)
+ if((retval = target_read_u16(target, flash_address(bank, 0, 0x00), &cfi_info->manufacturer)) != ERROR_OK)
{
return retval;
}
- if((retval = target_read_u16(target, bank->base + 0x2, &cfi_info->device_id)) != ERROR_OK)
+ if((retval = target_read_u16(target, flash_address(bank, 0, 0x02), &cfi_info->device_id)) != ERROR_OK)
{
return retval;
}
LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
/* switch back to read array mode */
cfi_command(bank, 0xf0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xff, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
* SST flashes clearly violate this, and we will consider them incompatbile for now
*/
cfi_command(bank, 0x98, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
{
cfi_command(bank, 0xf0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xff, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
* we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
*/
cfi_command(bank, 0xf0, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xff, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
return ERROR_FLASH_OPERATION_FAILED;
cfi_command(bank, 0x90, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
}
cfi_command(bank, 0xff, command);
- return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}
static int cfi_spansion_protect_check(struct flash_bank_s *bank)
int i;
cfi_command(bank, 0xaa, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x55, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x90, command);
- if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
+ if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
}
cfi_command(bank, 0xf0, command);
- return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}
static int cfi_protect_check(struct flash_bank_s *bank)